ADC calibration

[lpcware]

Content originally posted in LPCWare by Genesy on Tue Oct 15 06:22:02 MST 2013
Hi,
in the datasheet of LPC11xx and other I read that ADC without calibration is affect by a total error of about 4 LSB.
How I can do an ADC calibration to make my ADC most accurate?
If I reduce my adc sampling rate will I be most accurate?
I looked that this value is bounded with CPU frequency with the following formula:

PCLK/(CLKDIV+1)

where CLKDIV is a 8bit field in ADCR register.
Since I work at 48 MHz and the maximum value is 256 CLKDIV the ADC minimum frequency is 187500 khz, is right?
Isn't this a limit?

Thank you very much

[lpcware]

Content originally posted in LPCWare by tha on Thu Oct 17 15:56:09 MST 2013
There are different way to calibrate an ADC.  The white paper from the EDN article on ADC offset and gain provides a good idea on how to calibrate for these two parameters.

http://www.edn.com/contenteetimes/documents/schweber/c0976/c0976edited.pdf
http://www.edn.com/contenteetimes/documents/schweber/c1000/c1000edited.pdf

Slowing the ADC sampling speed will, in most cases, increase the accuracy of the ADC measurement.  But, because the sampling speed is slower, the voltage being sample must be keep stable during the sampling time.   Also the bandwidth of the ADC will be lower.