Content originally posted in LPCWare by graynomad on Thu Sep 29 02:07:27 MST 2011
I've looked at XMOS a few times but still don't quite get it. There doesn't appear to be any peripheral devices, do you bit bang everything?
I can see it being good for my trigger state machine, or something simple and fast, but not suitable for a main processor because of the limited memory.
Can you use assembler?
If I use external hardware I should be able to get 50MHz, but let's stay with the original brief of 25MHz.
The fastest loop I can think of (outside using ASM) is something like this
while (1) output_pin = 1;
On an AVR that will toggle the pin every time and the loop will take maybe 2-3 cycles. But obviously absolutely nothing else can happen including interrupts.
With hardware timers such as on the LPC I'm reasonably happy I can get 25MHz but with all the other stuff that needs doing and the indeterminate DMA timing I've now decided that external hardware is the way to go.
Essentially I need to do two things
a) 19-bit synchronous counter for external RAM address
b) 24-bit magnitude/equality comparator and state machine for triggering
The counter would be a no-brainer with a CPLD/FPGA.
The trigger comparator and state machine will be a challenge with any technology if high speed is required. With hardware of course the comparison and state machine stuff will be lightning fast but my brain hurts just thinking about the FPGA design.
On the other hand I can see it would not be too difficult in software.
Presently I'm considering dedicating an LPC111x to this job. At 50MHz I reckon I can do the job in 1uS or less, in which case I just state in the manual that when using complex triggers the trigger state has to be stable for at least 1uS.
Now using the XMOS I get 2x the raw speed plus multiple threads as well. So can one thread look at the 24 bits and do the magnitude comparison on 12 of them. Another thread looks at the other 12 bits and does an equality comparison. They both set flags on common memory.
A third thread reads these flags and starts a timer when both are true.
If the timer times out and the flags are still both true we have trigger event.
With 2x the clock and 2 threads at the sharp end maybe I can detect an event with 250nS resolution which is 4x what I could do with an LPC111x.
Is it worth learning a new processor architecture for that?
Probably not if that's all I get, but if the XMOS can replace all the other hardware MUXes, counters etc and save me from using CPLD/FPGAs then maybe.
Can you point me to some proper documentation, I can find nothing that resembles a normal data sheet on the XMOS site.
______
Rob
