what are the actual memory ranges for the dynamic chips selects?

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what are the actual memory ranges for the dynamic chips selects?

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Contributor I

In the LPC546xx user manual, in table 634, address ranges for the different chip select pins are listed.  But, the address ranges for at least the dynamic cs's are first not big enough for the range listed.  second, they do not match what is shared in LPC54608.h:

/** EMC CS base address */
#define EMC_CS0_BASE (0x80000000u)
#define EMC_CS1_BASE (0x90000000u)
#define EMC_CS2_BASE (0x98000000u)
#define EMC_CS3_BASE (0x9C000000u)
#define EMC_DYCS0_BASE (0xA0000000u)
#define EMC_DYCS1_BASE (0xB0000000u)
#define EMC_DYCS2_BASE (0xC0000000u)
#define EMC_DYCS3_BASE (0xD0000000u)
#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}

and the UM:

pastedImage_1.png

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NXP TechSupport
NXP TechSupport

Hi Eileen Radzwion

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
As you mention out, there's some errors and contradictions in the memory mapping, I'll contact the AE for checking and reply you later.

Have a great day,
TIC

 

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Contributor I

Hi Jeremy, is there any update on this?

thanks!

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NXP TechSupport
NXP TechSupport

Hi Eileen Radzwion

The AE team has confirmed these errors, however, I'm still waiting for their conclusion about correct EMC memory mapping.
Please be patient, thanks.

Have a great day,
TIC

 

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NXP TechSupport
NXP TechSupport

Hi Hi Eileen Radzwion,

According to the AE's reply, the head file: LPC54608.h is correct, so the correct memory mapping is illustrated below.

Hope this is clear.

pastedImage_1.png

Have a great day,
TIC

 

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