Hi pascal carreweyn,
Thanks for your reply.
It seems a bit weird, so please confirm that the correct address areas are written.
I was wondering if you can share a compile-able demo which can replicate this phenomenon, then I can do some testing on my site.
Have a great day,
TIC
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Dear Jeremy,
Now the pio0 6 and pio 07 are configured as uart, the problem was the wrong address.
But now my previous problem stays !!!
The piece of code underneath doesn't effect the UART1 registers at all ? What could be the reason of this ? I just changed the UART0 to UART1 and if i debug i can see the addresses are right...
Chip_UART_Init(LPC_UART1);
Chip_UART_SetBaud(LPC_UART1, 9600);
Chip_UART_ConfigData(LPC_UART1, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT));
Chip_UART_SetupFIFOS(LPC_UART1, (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2));
Chip_UART_TXEnable(LPC_UART1);
I also thought there would be a wrong address but it seems to be something else ?
in the chip.h we have
#define LPC_UART0_BASE 0x40008000
#define LPC_UART1_BASE 0x40020000
#define LPC_UART2_BASE 0x40024000
...
#define LPC_UART0 ((LPC_UART_T *) LPC_UART0_BASE)
#define LPC_UART1 ((LPC_UART_T *) LPC_UART1_BASE)
#define LPC_UART2 ((LPC_UART_T *) LPC_UART2_BASE)
in the uart_112x.h we have
/**
* @brief UART register block structure
*/
typedef struct { /*!< UARTn Structure */
union {
__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
};
union {
__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
};
union {
__O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
__I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< Modem Control Register. Only present on UART ports with full modem support. */
__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< Modem Status Register. Only present on UART ports with full modem support. */
__IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
__I uint32_t RESERVED0;
__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
__I uint32_t RESERVED1;
__IO uint32_t TER; /*!< Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
__I uint32_t RESERVED2[6];
__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
} LPC_UART_T;
/**
Any idea what's going on ?
