stereo I2S and DMA issue

[lpcware]

Content originally posted in LPCWare by ameares on Mon May 05 15:38:31 MST 2014
I am having a problem with transferring stereo audio data from the I2S peripheral to memory on my LPC1766FDB100 chip.  I have a seen a few posts regarding I2S and DMA, so maybe someone out there will have some experience that can help me out or maybe we can replicate the problem.

I have a program that is transferring 32-bit stereo data from the I2S peripheral to memory.  I use the TC interrupt to set up the DMA transfers.  Sometimes my program has to pause the DMA transfers for a few milliseconds to perform an unrelated bit of code.  I just want to throw away the I2S data for a little while and when I am ready, start transferring data again.  So, every once in a while when I restart the DMA, it doesn't start on the left channel.  I would guess this is 1 in 100 or 1 in 1000 times that the transfer is restarted after missing a few 10s of milliseconds of samples.  I have tried stopping and resetting the I2S periphal using its I2SDAI bits.  Still it seems that almost randomly the left and right channels get confused.  I would guess that there is a small possibility that if I powered on my project 1000 times, it would get the left and right channels mixed up at least once.  This is turning into a bit of a problem.

I realize this is difficult to explain.

Is there a specific procedure for stopping peripheral to memory DMA and the I2S receiver for some time and then restarting it?

Is there any possibility that the left and right channels on 32-bit DMA transfers could get misaligned for any reason?

Thanks,
Andrew, MidNite Solar

[rsk2]

I am having the same problem with LPC5526 and LPC55S69 right now. Did you find a solution to L/R I2S channel swapping? I wonder if the DMA is missing interrupts or getting confused?

[lpcware]

Content originally posted in LPCWare by ameares on Mon May 12 10:01:40 MST 2014
I still have not found a solution to this problem.  Stereo 32-bit I2S using peripheral to memory DMA is causing the left and right channels to get swapped occasionally when DMA is restarted.  I have been trying to figure out what the proper I2S burst request fifo buffer level and DMA burst size settings are and it may have something to do with this issue.

Would it help anyone if I posted some code here?

[lpcware]

Content originally posted in LPCWare by boB on Wed May 07 15:46:22 MST 2014
Does nobody else use the I2S with DMA and stereo A/D -- D/A   with these processors ?