spifi 18xx

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spifi 18xx

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by coco on Wed Sep 11 00:35:05 MST 2013
Hi guys,

has been trying to port the sample spifi keil project to xpresso project (for LPC1830 board) and encounter some problem,
* spifi_drv_M3.lib , how do convert this .lib to .a? or is renaming the file to .a good enough?
* how to load this .lib to ram? I tried to rename the .lib to .a and the compilation pass, but it hangs at spifi_init(). I suspect it's because I need to load this function to ram.
  I added this to my .ld file but from the map file, it doesn't seem to be correctly loaded to RAM
.data_func : ALIGN(4)
{
   FILL(0xff)
           libspifi_drv_M3.a (.text)
   . = ALIGN(4) ;
} > RamLoc96 AT>RO_MEM

* also tried the driver recommended by this thread: http://www.lpcware.com/content/forum/spifi-errata-and-part-version-information#comment-1023028 , but it hangs at this line:
  SCnSCB->ACTLR &= ~2; // disable Cortex write buffer to avoid exceptions when switching back to SPIFI for execution

Thanks!





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930 次查看
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by coco on Thu Sep 12 02:23:13 MST 2013
The 1830 that I'm using is Cortex M3.

Edit:
For verification, I compiled the original sample code (from lpcopen) with keil and it can run with no issue. But once, I ported that project to xpresso , it just hangs at the spifi_init. It really looks like a porting issue, but the code is so straightforward that I don't know where to look. Anyone manage to compile+run this code with xpresso / gcc?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by noahk on Wed Sep 11 15:44:11 MST 2013
Hi coco,

The spifi xip storage example is not a complete driver. It illustrates some spifi usage and hopefully will ease the process of writing a suitable driver for your application. The SCnSCB write is meant to disable the cortex write buffer. Perhaps the chip you are using doesn't have this bit. I believe this bit exists on the M3 and the M4, but not the M0 or M0+. This was written for the LPC4350, and you are using an 18xx (not sure which exactly). Can you check the which Cortex the chip has?

Noah
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