setting BD rate upper than 115200 for uart in lpc812

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

setting BD rate upper than 115200 for uart in lpc812

2,761 Views
mahmoudhosseini
Contributor III

I'm using below LPCOPEN based codes for configging UART on my LPC812.

for normal baud rate below 115200(most usual) it works fine,but when i set a custom baud rate like(115200 *2) or

(115200 *n) it does not work either.whats problem?

  //---UART Initialing---------------------------------

Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);

 

/* Divided by 1 */

Chip_Clock_SetUARTClockDiv(1);

 

/* Connect the U0_TXD_O and U0_RXD_I signals to port pins(P0.4, P0.0) */

Chip_SWM_DisableFixedPin(4);

Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4);

Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0);

 

/* Disable the clock to the Switch Matrix to save power */

//Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);

Chip_UART_Init(LPC_USART1);

Chip_UART_ConfigData(LPC_USART1, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);

Chip_Clock_SetUSARTNBaseClockRate((115200 * 16), true);

Chip_UART_SetBaud(LPC_USART1, 115200);

Chip_UART_Enable(LPC_USART1);

Chip_UART_TXEnable(LPC_USART1);

Labels (2)
Tags (4)
4 Replies

1,833 Views
rolfmeeser
NXP Employee
NXP Employee

I can see two options to get to higher baud rates:

  1. The UART fractional rate generator in the SYSCON block supplies the input clock globally to all UART's by dividing down from the main clock. Assuming a main clock of 24 MHz, the total prescaler ratio for a baud rate of 230400 is 24M/(230k4*16)=6.51. This can be distributed over the integer prescaler (global), the fractional generator (global), and the integer baud rate generator (per UART).
    As an example, set UARTCLKDIV=2 (divide by 2), USART0.BRG=2 (divide by 3). The fractional divider must be set to 6.51/6=1.0851, which is achieved by UARTFRGDIV=255 (DIV=256), UARTFRGMULT=22.
    The resulting baud rate is 230216 (-0.08%)
  2. In general main clock is not equal to CPU clock. While the CPU clock is limited to 30 MHz, the main clock can be as high as 100 MHz. Example: Set the PLL to provide a main clock of 48 MHz, then divide by 2 (SYSAHBCLKDIV) for a CPU clock of 24 MHz. Now the 48 MHz can be divided by 13 to get an accurate 230400 baud rate. Doesn't require the fractional generator in this case.
0 Kudos
Reply

1,833 Views
DavidS
NXP Employee
NXP Employee

Hi Mahmond,

I am not expert but a quick testing using LPCOpen for LPC812MAX board and Example_UART0_Terminal example shows the core clock is set to 24MHz and default baud is 9600.

Changing the BRG value from 155 to 12 allowed the baud to work successfully at 115200.

But trying to double it to 230400 baud did not work (I set BRG=5).  But I believe the reason is too much error as the calculated BRG was 5.5 and rounding it to nearest integer didn't work.  However increasing to 249600 baud had calculated BRG ~5 and that worked fine for me using Putty as my PC terminal utility.

  // Configure the USART0 baud rate generator

  LPC_USART0->BRG = 5; //DES was 155;  155 for 9600 baud and 12 for 115200 baud, 10 for 134400 baud

             //DES 9 for 153600, 7 for 192000 baud, 6 for 211200 baud, 5(5.5 calculated) for 230400 baud...NOT WORKING

             //DES 5 for 249600 baud....WORKING

             //DES Summary:  Too much error in UART clock config when core at 24MHz to achieve 2*115200 baud.

Regards,

David

1,833 Views
mahmoudhosseini
Contributor III

Dear David,

Really thanks for your great help,

is there any calculator tools which be able to calculate register values & error for custom baud rates?

0 Kudos
Reply

1,833 Views
DavidS
NXP Employee
NXP Employee

Hi Mahmoud,

You are welcome.

Sorry there is no calculator that I know of.

Regards,

David

0 Kudos
Reply