LPC_ADC->ADCR = 0; // Power AD down LPC_SC->PCONP |= (1 << 12); // Enable power to AD block LPC_SC->PCLKSEL0 &= ~(1<<24); // clock 25 MHz LPC_SC->PCLKSEL0 &= ~(1<<25); LPC_ADC->ADCR = 7 << 8; // conversion clock = 100 Mhz / 8 [7+1] = 12.5 MHz LPC_ADC->ADCR |= (1<<21); // PDN = set AD operational LPC_ADC->ADCR |= (1<<0); // SEL = select AD0.0 to start int Good = 1; int Bad = 0; while(1) { LPC_ADC->ADCR |= (1<<24); // START = start conversion now while (!(LPC_ADC->ADGDR & ( 1UL << 31))) ; /* Wait for Conversion end */ int value = (LPC_ADC->ADDR0 >> 4) & 0xFFF; if((value < 0x580) || (value > 0x5FF)) Bad++; else Good++; double pct = (double)Bad * 100 / (double)Good; Debug("AN0 = %X good %5d bad %5d %.02f%%", value, Good , Bad, pct); os_dly_wait(25); } |