Content originally posted in LPCWare by bavarian on Fri Sep 27 08:59:00 MST 2013
The dual core project in the µVision installation is a good starting point:
.\Keil\ARM\Boards\Keil\MCB4300\DualCore
However, if you want to create a project on your own just follow this guideline:
1. Create a µVision project for a Cortex-M0
- use an ARM Cortex-M0 as target and not the LPC4357 from the list of NXP devices (Cortex-M0_TargetSettings.png)
- the code for the M0 can be located anywhere in memory, the easiest setup is one of the flash internal flash banks (here in bank #B)
- allocate some RAM for the M0 code (any area works)
- make some settings for output folder etc etc
- make the correct setting for the debugger and the flash utility (Cortex-M0_DebugSettings.png , Cortex-M0_FlashUtilitySettings.png)
- write your code(startup.s for the M0 in the LPC4300 + any other files), compile, download to flash. Maybe just reconstruct the project from KEIL, but now running from flash instead of RAM
2. Create another µVision project for an LPC4357
- use the LPC4357 from the list of NXP devices (Cortex-M4_TargetSettings.png)
- the code for the M4 can be located anywhere in memory, the easiest setup is one of the flash internal flash banks (here in bank #A)
- allocate some RAM for the M4 code, take care that it doesn't conflict with the area for the M0
- make some settings for output folder etc etc
- make the correct setting for the debugger and the flash utility (Cortex-M4_DebugSettings.png , Cortex-M4_FlashUtilitySettings.png)
- take also attention to the user settings (Cortex-M4_UserSettings.png), the M4 code for the internal flash needs to have a signature, done with the tool ELFDWT.EXE
- write your code (startup.s for the M4 in the LPC4300 + any other files), compile, download to flash. Maybe just reconstruct the project from KEIL.
So far no real problem right?
Now you need to know that the chip comes out of the bootloader process with the Cortex-M4, the M0 is held in reset.
Whenever you would like this to happen in your M4 code, you need to make two settings for the Cortex-M0 to start it:
// The M0a has no Vector Table Offset Register. From the M0a point of view the vector table is fixed at 0x00000000.
// So the M0a memory map starts at 0x00000000, but the shadow pointer must point to the physical memory in which
// the M0a code resides.
LPC_CREG->M0APPMEMMAP = 0x1B000000;// Set M0a shadow pointer to flash bank #B.
// Release M0a from reset by clearing bit 24 in register RESET_CTRL1
while(!(u32REG & (1u << 24)))
{
u32Val = (~(u32REG) & (~(1 << 24)));
LPC_RGU->RESET_CTRL1 = u32Val;
u32REG = LPC_RGU->RESET_ACTIVE_STATUS1;
}
Then you have both the Cortex-M4 and the Cortex-M0 running. There are a lot of nitty-gritty details now how to do things best, how to communicate between the two cores, how to do dual core debugging (if this is really needed) etc. But here it's best to look into the dual core examples in the LPCopen software package.
Hope it helps a little bit,
NXP Support
