how LPC55 change PLL out wile PLL is running

[qingyunliu]

Does LPC55 has regs like RT685's 'CLKCTL1_AUDIOPLL0NUM', that can change PLL.

[qingyunliu]

thanks for your reply, but I guess FRG reg is a wrong regs to change PLL.

In LPC55, use FRO as source of PLL0, and attach PLL0 clock to MCLK for I2S.

Dose it means if I change FRO, then I2S clock will be change too?

So I want ask which registers can be modify if I want change FRO?

FRO_192M_CTRL? you can see the examaple in usb_examaple/usb_device_composite_hid_audio_unified.

[xiangjun_rong]

Hi,

The FCLKx pin(FCLK of Flexcomm[n]) is the only I2S driving clock, if you set the following clock divider register as 0, the FCLKx is the I2S bit clock.

So you have to select the FRGx input source to select the I2S clock.

Hope it can help you

BR

XiangJun Rong

[qingyunliu]

hi xiangjun,

thanks for you reply，hope you can explain my question directly.

use FRO as source of PLL0, and attach PLL0 clock to MCLK for I2S.

[Q1]. Dose it means if I change FRO, then I2S clock will be change too. FRO_192M_CTRL? If I change bit16-23, what will happen?

best regards

[qingyunliu]

I checked regs FRO_192M_CTRL, how  can I verify this regs? 

the following log shows FRO_192M_CTRL 'DAC_TRIM' can be changed.

but the SDK following API 'pllRate' means what? If I change FRO_192M_CTRL. does real PLL out will be changed?

[xiangjun_rong]

Hi,

As the following pic, the the FCLKx is the only clock which drive the I2S module as bit clock.

Assume that you use 48KHz sampling frequency, and 32 bits for each slot, and use 2 slots, the I2S bit clock will be 32*2*48KHz=3.072MHz

If you use 12MHz FRO, and set the I2S clock divider as 4, the FCLKx divider must be 12Mhz/(4*3.072MHz)=0.9765625

1/(1+mult/255)=0.9765625

so the mult will be 6.12, you truncate it as 6.

The actual I2S bit clock frequency will be:

12MHz/[(1/(1+6/255))*4]=3.075MHz

If you use main_clk as 150MHz, you can use it to get about 3.072MHz I2S bit clock, pls compute the I2S divider and MULT bits in FRG.

Hope it can help you

BR

XiangJun Rong

[qingyunliu]

thanks for your reply.

what I mentioned is FRO/PLL clock instead of I2S clock.

in demo LPC55S/.../dev_composite_hid_audio_unified_lite 

[Q1] if I change FRO192M_CTRL, does it means FRO12/PLL0/I2S clock will change too?

[Q2] as you can see, CTIME1 's soure clock is FRO_HF, if I change FRO192M_CTRL, will cause Ctimer  count change too?

best regards

[xiangjun_rong]

Hi,
The clock system of i.mxrt600 and LPC55xx are different, the LPC55xx has two PLL: PLL0 and PLL1, both the PLL0 and PLL1 can times the clock to provide clock for the core and peripheral.

As the following picture I copied from UM11126.pdf which is UM of LPC556x/552x. From the pic, you can see that the FCLK is the clock of I2S module via a divider by I2S module, the FLCK can drive the I2S as bit clock via a divider. The FCLK source can be from main_clk which drives the core and peripherals, the MCLK_IN, which is dedicated audio clock from external pin, pll0_clk_div is the divided  PLL output clock. The FRO12 is the 12M internal clock.

The FRG can function as a divider, which can divide the source clock by divider range from 1.0 ... 2.0 in fractional way.

Pls tell us your application and the audio clock requirement so that we can help you

BR

XiangJun Rong