fsl_mcan losing interrupts

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fsl_mcan losing interrupts

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teus
Contributor I

Hello,

We use the fsl_mcan driver below our CANopen stack and the driver is not handling interrupts correct.

  • We see that the sometimes when interrupts handler is called the interrupts are not correctly copied from the IR register. When we set a breakpoint behind this copy the IR register is filled with interrupts and the variable is zero.

The problem is that after a few minutes the driver stops with sending messages because the cancellation is not finished. The driver comes back when the first bit in the TXBAR register is set. The adds a new request which clears all the pending flags when finished and runs again for a while until it happen again.

So far we changed the interrupt handler that only the handled interrupts are cleared. And we added the following in the handler of the Tx complete:

pastedImage_2.png

This delays the problem. Without the above fix it will last an hour and otherwise it will last a few minutes.

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teus
Contributor I

FYI,

We figured something out and that is solving this problem.

We have seen that sometimes the interrupt handler was called with the IR register not set. Probably that are the tx interrupts that we are missing.


We added the following code in the interrupt handler:

pastedImage_1.png

The implementation of the MCAN_FinalizeTransmit function is as follows:

pastedImage_4.png

To be completely sure we also call MCAN_FinalizeTransmit when an rx interupt occurs.

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Alexis_A
NXP TechSupport
NXP TechSupport

Dear Teus,

I have some question regarding this issue.

Which baudrate are you using?

Which is the state of the FIFOs when this error appears? Is it full?

Which is the value of the error counter register (ECR) when this error appears?

Best Regards,

Alexis Andalon

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teus
Contributor I

Dear Alexis,

Thanks for your help at first.

  1. The baudrate that we are using is 250 kbits
  2. We are not using the FIFO's of the pheripheral. We only use 1 transmit register and wait until that register is done before we send the next packet through the same register. 
  3. The value of the register ECR is 0

For more information about the register see the screenshots in the appendix / below. CAN1 is the pheripheral with the problems. The screenshots are taken on the moment the problem happend.

Best Regards,

Teusscreenshot_can_1.pngscreenshot_can_2.png

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Alexis_A
NXP TechSupport
NXP TechSupport

Hi Teus,

As I could check in the registers of the CAN1 you have a FIFO with size of eight elements, and is full in the moment in which the error is present. Check the RXF0C and the RXF0S to confirm this information.

So I think something is wrong with the stack you're using. I will suggest to put a watermark in the FIFO and enable the interruption to see when this being filled more that what you want.

Best Regards,

Alexis Andalon

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