Content originally posted in LPCWare by Sal Ammoniac on Tue Nov 25 09:20:42 MST 2014
I'm writing a driver for the LPC4300 SSP0/1 and noticed that the transmit and receive interrupts are only triggered when the eight frame transmit and receive FIFOs are at least half full (RX) and half empty (TX), or when an RX timeout occurs (32 bits at the current SSP clock rate).
This makes it difficult to handle small (<4) frame transfers without either polling for completion or waiting for the RX timeout period to elapse. Anyone have any ideas for dealing with this? I have a few SPI peripherals that transfer small amounts of data (less than half a FIFO's worth), but I don't want to stall the CPU polling for completion or the application by waiting for an RX timeout interrupt.
It seems to me that the designer of the 43xx series SSP peripheral could have easily made the RX and TX interrupt trigger points configurable and not just hard coded to happen when the FIFOs are half full/empty. There are plenty of unused bits in the SSP interrupt mask register, and the additional logic would not have amounted to more than a few gates. This kind of thing makes writing drivers for these chips a pain in the bum.
