Understanding timer interval values for match register

[lpcware]

Content originally posted in LPCWare by micro9000 on Fri Aug 09 23:26:28 MST 2013
Hey guys I could use some help understanding the timer example provided. I am using the LPC1764 running at 100MHz and using LPCXpresso 5.2.6.

In the LPCX176x_cmsis2_timers example I see the following code:

#define TIMER0_INTERVAL((2 * (4 *(SystemCoreClock/10))) - 1)
#define TIMER1_INTERVAL((2 *(4 *(SystemCoreClock/10))/3) - 1)
#define TIMER2_INTERVAL((2 *(4 *(SystemCoreClock/10))/5) - 1)
#define TIMER3_INTERVAL((2 *(4 *(SystemCoreClock/10))/7) - 1)

My question is how are these values calculated. For instance:

(2*4*100MHz)-1 => ~800x10^6 or 800 million. Is this 8 seconds? Also, why is the 2*4 necessary? If someone could explain to me the calculation of the intervals and how the match register will use this value it would be much appreciated.

[lpcware]

Content originally posted in LPCWare by Ano on Tue Jul 22 17:07:16 MST 2014
Now i get it. Pretty simple in fact... Don't know why it confused me.
Big thanks!

And what's the resolution of the variable Frequency then? ^^

[lpcware]

Content originally posted in LPCWare by LabRat on Tue Jul 22 16:22:28 MST 2014
:quest:

If your timer is running with:

f(timer) = SystemClockRate/4

and match = SystemClockRate/80

It's generating (toggling = /2):

f(match) = (SystemClockRate/4)/(SystemClockRate/80)/2 = 80/4/2 = 10 Hz

[lpcware]

Content originally posted in LPCWare by Ano on Tue Jul 22 15:42:17 MST 2014
I have a problem with the same thing. I'm using the LPCxpresso 1769 with a 120MHz quarz.
My measured values for the toggle-frequencies are:
SystemClockRate/80 = 10 Hz

(Working with the timer and match "Chip_TIMER_SetMatch(LPC_TIMER0, 0, (Chip_Clock_GetSystemClockRate()/80))")

So, how is the formula to calculate these frequencies?

(SystemClockRate / 80) * 2 * 4 = ?
(first *2 for the 2 toggles to create one period, second *4 for the divided clock timer)
But this would make (120MHz / 80) * 2 * 4 = 12000000 Hz

[lpcware]

Content originally posted in LPCWare by micro9000 on Sun Aug 18 13:58:07 MST 2013
Thank you. It makes sense to me now.

[lpcware]

Content originally posted in LPCWare by NXP_Paul on Fri Aug 16 11:03:57 MST 2013
I'm not sure why the timer intervals were defined as shown in the example code, but I can tell you what you can expect if programmed with these values.
A timer loaded with SystemCoreClock/x will generate a timing internal of 1/x seconds.  In the example above, the value SystemCoreClock/10 will give you a timing interval of 0.1 seconds, while SystemCoreClock/5 would give a timing interval of 0.2 seconds. You will see this way of defining a timing interval quite often in example code because it provides a very simple way of defining the timing interval, and the timer interval will remain constant even if you change the clock value.
I can only guess that the "-1" was appended to the end of the define statement since the example uses interrupts, and interrupts are triggered one clock cycle after the timer match occurs (see Figure 114 in user manual UM10360).
By default, the clock to the timers are actually divided by four (see the PCLKSEL0 and PCLKSEL1 registers in the user manual), so they aren't being clocked at SystemCoreClock, unless you change the value in the PCLKSEL registers.
Therefore, assuming a SystemCoreclock=100MHz, you would get the following:
TIMER0_INTERVAL = ((2 * (4 *(SystemCoreClock/10))) = (2 * (4 * (0.1 sec)))  = 0.8 seconds, but since the clock to the timer is divided by four, the actual time interval is 3.2 seconds.
The LED will therefore blink once every 6.4 seconds.