Content originally posted in LPCWare by okwh on Sat Dec 19 21:13:28 MST 2015
yes, you are right. all OK if I use software mode.
but LPC54102 has 4+4 SPI for two SPI port, I will use 4+3 with different SCK rate and all master mode
so lot of SPI needed, if I use software simulate mode, not only need a lot of IO codes ,but also need a lot of time to debug and adjust their IO rate and time period.
LPC54102's SPI TXdata is 1~16 bits per pack(frame, or group). more bits data need to be splited in to more parts. But now I find de-assert the SSEL which is not allowed !
below is the states shown in manual:
23.7.6 Data lengths greater than 16 bits
The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames of any size, including greater than 32 bits, can supported in the same way.
Details of how to handle larger data widths depend somewhat on other SPI configuration options. For instance, if it is intended for Slave Selects to be deasserted between frames, then this must be suppressed when a larger frame is split into more than one part. Sending 2 groups of 12 bits with SSEL deasserted between 24-bit increments, for instance, would require changing the value of the EOF bit on alternate 12-bit frames.
I needed is Sending 2 groups of 8 and 16 bits with SSEL DEASSERTED between 24-bit increments
but now I find SSEL DEASSERTED between 8 and 16.
Is it possible whether SSEL DEASSERTED related with time-wait between 8 and 16?
Without EOT, should be no SSD, how to judge 1st pack has been sent out ?
maybe I have to use software simulate mode