Content originally posted in LPCWare by PhilYoung on Fri Apr 13 09:49:06 MST 2012
the latest demo code provides some more detailed functions for this, as used in the fastboot example.
The problem however is computing some of the other values for setting up the PLL, particularly if you need to set up the audio or USB PLL, I can't find the algorithm for these but there is a program from NXP to compute them and provide the values to write into the registers.
Also, when updating the core clock you need to be careful about switching directly to a high speed since this can crash the device ( due to a bug that still hasn't made it into the errata ), you may need to switch frequency in stages or the CPU may crash.
personally I chose not to use the supplied functions since they build a cross reference table of frequencies and legal options and test everything, this has a significant RAM overhead and is completely unnecessary in most embedded systems where the frequency plan is determined once and fixed for the application lifetime.
Setting up the clocks then just needs a few lines of code.
regards
Phil.