Content originally posted in LPCWare by riscy00 on Mon Jan 06 00:08:34 MST 2014
Hi
I could not get equation working correctly, I have XTAL = 8MHz and Target SystemCoreClock is 100Mhz (or close to this)
After complies and run, the SystemCoreClock provide 100.480Mhz which is okay for this application, but when I check with equation in UM10360...
#define PLL0CFG_Val 0x0004009C// This provide 100,480,000 Hz according to SystemCoreClock
#define CCLKCFG_Val 0x00000004// Divide Value for CPU Clock from PLL0 FCCO/4 = 100.48MHz as required.
N +1= 5 and
M+1 = 9D = 157
CCLKCFG=4 (post PPL divided = 4)
FIN = (Fcco*N)/2*M)
100.480MHz * 4 = 401.92Mhz = Fcco, then Fin = (401.92Mhz * 5) / (2 * 157) = 6.4MHz…..could not compute to 8Mhz!!.
Have I missed something?