Still reading but looking for clarification on AHB

[lpcware]

Content originally posted in LPCWare by tvink on Thu Jan 29 08:55:41 MST 2015
Posting this will help me sort this stuff out in my own understanding... and hopefully may pull in some useful responses.  ...or corrections.


If I am reading correctly...

The AHB matrix has no programmable features.  It simply is a hardware means of connecting 9 masters to 9 direct slaves and a bunch of bridged slaves.  It gives priority to the LCD master and then the system bus followed by the instruction/data buses and then the rest. 

-- What stuff goes on the system bus?

The bridges also do not have a programmable interface.  They simply move data between resources and the AHB bus using a hardware determined priority scheme.

Code written for the MCU does not need to be aware of the AHB... except for perhaps some provisions dealing with the fixed priority ordering which would matter when a 2nd master may be vying for a resource.  If contention occurs when accessing a resource there may be a stall in the MCU pipeline while higher priority masters are connected to the resource.  Software written so that this is not statistically likely will be fine.

On each bridged segment, if there is no DMA accessing the attached resources, the bridge has no impact in performance.  In this case the MCU is the only master accessing the resources and can only access one resource at a time anyway.

-- Do each of the masters have their own internal DMA controller?
   The GPDMA is used to move data between slaves like SPI with SRAM, UART with SRAM, etc.   ...or even UART to DAC.

After writing all that I am not really sure what bridges are doing anyway.  Here is my guess.  The AHB matrix is multilevel so multiple transactions can occur simultaneously.  Multiple masters may be accessing slave resources at the same time.  As long as they do not try to access the same resource at the same time, there will be no contention.   However each bridged segment can support only one transaction at a time.  So if the MCU wants to access USART2 at the same time that the GPDMA wants to access USART3 there will be a stall for the lower priority master.  yes?

-- What is local SRAM and AHB SRAM.  I would guess that the LOCAL one is not on the AHB matrix.  But both are shown as a slave in the MCU block diagram.  I would have expected the local SRAM to be inside the MCU box.  Do I have that right?

Thanks in advance for any helpful illumination....

[lpcware]

Content originally posted in LPCWare by starblue on Fri Jan 30 02:47:43 MST 2015
Interesting.

It seems the EMC got those 4 ports just to override the default priority scheme of the AHB. I understand why they put LCD as the top priority, but not why there are three more priorities and why they are in this order.

[lpcware]

Content originally posted in LPCWare by tvink on Thu Jan 29 11:01:08 MST 2015
you are right...

It is the EMC that has this priority scheme for connecting to bus masters. 


Thanks

[lpcware]

Content originally posted in LPCWare by starblue on Thu Jan 29 09:59:58 MST 2015

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Quote: tvink

The AHB matrix [...] gives priority to the LCD master and then the system bus followed by the instruction/data buses and then the rest. 

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Where did you read that? My UM10470 says in 2.6 AHB multilayer matrix configuration: "a round robin arbitration scheme is used".

On LPC17 priority is configurable.

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Quote: tvink

-- What stuff goes on the system bus?

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Most accesses from 0x20000000 and up (except some on the private bus of the core).

Joseph Yiu's "The Definitive Guide to ARM Cortex -M3 and Cortex-M4 Processors" has a chapter on the memory system.

You could also look through the documents on Cortex-M from ARM, though I'm not sure which document you need (this hasn't been my focus yet).