Content originally posted in LPCWare by diederikloos on Sat Dec 12 02:17:22 MST 2015
I found the solution for this problem. It has to do with S25Fl512S.
I found that toggling quad mode caused the bytes to shift as well. Then i started looking at the datasheets more thoroughly, and i found that there are latency codes included (latency codes depict how many dummy cycles there are between the address and the actual data during a read command). Basically, what happened was that the writing to flash succeeded, but when reading, there were one or multiple dummy cycles included, causing the data to shift 1 byte. In the spifilib, there is another spansion chip mentioned, where the latency bits are set to zero when initializing the device. By writing 2 zero's to the 14th and 15th bit of the status register, i disabled this latency mode, and suddenly the memory was alligned again. Hope this helps anyone else who might have the same problem in the future.
