SYSAHBCLKCTRL

[ianbenton]

I'm just migrating my code from LPC1517 to LPC5502 (because that's all I can get). LPC8, LPC11, LPC13 and LPC15 all require bits to be set in SYSAHBCLKCTRL in order to enable any particular peripheral.

The LPC5502 appears not to have a SYSAHBCLKCTRL register - what takes it place?

It is only mentioned in the manual in Fig.86 "Watchdog timer clocking".

[ianbenton]

Found it - it's AHBCLKCTRL - I was looking for something that started with SYS.

[ianbenton]

But that means that the reference in the watchdog timer section must be wrong?

[nxf77486]

Hello @ianbenton ,

Chapter 29 in the User Manual, show the basic configuration for the watchdog the is the following:

• Configure WDTCLKDIV register. See Table 103. Release the reset, disable HALT bit

and program DIV[5:0].

• Enable the register interface (WWDT bus clock): set the WWDT bit in the

AHBCLKCTRL0 register, see Table 55.

• For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up using low power API.

The AHBCLKCTRL0 bit for the WWDT has to be enable, please give me more information  why this could be wrong.