SSP0 Receive FIFO in LPC11U68J100

[jeanvaljean]

Gentlemen,

is it possible to see somehow in LPCXpresso the receive FIFO of LPC11U68J100 controller?

I'd like to check it, because I don't have the same data in SSP0_DR  what the master sends. The uC is configured as slave. I got the SSP0 interrupt, something comes in but not what I expect.

Signals are checked by oscilloscope, they're correct. I should have some SW issue there.

In case my uC is slave, should the internal SSP0 clock have exactly the same frequency, as the master has?

The chip is on OM13058 LPCXpresso board, I use LPCXpresso 8.1.4 on Win7.

[lpcxpresso_supp]

The Peripheral View should give you access to the Status Register (which will tell you if the FIFO is empty or full),  but I don't think this will give you access to the actual FIFO itself (unless it is exposed in the memory map).

You might get more focused advice from the LPC community (for hardware usage) rather than the LPCXpresso IDE one - which is focussed more on tools usage. So I'll transfer your question there.

Regards,

LPCXpresso Support

[jeanvaljean]

Ladies and gentlemen,

nobody knows the answer of these questions?