SSP Slave Problem on LPC11E14

[lpcware]

Content originally posted in LPCWare by qinnoNxp on Mon Dec 01 00:52:06 MST 2014
Hallo,

I would like to use my LPC as a SPI-Slave. It seems to be configurated right. But I only receive one byte. So the master has to toggle the SSEL after every byte.
Is there any solution or workaround?

Link to someone having the same problem on the lpc1769:
http://www.lpcware.com/content/forum/problem-with-ssp-on-lpc1769

Please help me.
Best regards.

[lpcware]

Content originally posted in LPCWare by 1234567890 on Tue Dec 02 10:07:34 MST 2014
Just have had a short look at the code (which doesn't seem to be copy&paste):

while((LPC_SSP1->SR & (1 << 2)) && bufferpos < length-1)
{
buffer[bufferpos] = (BYTE)LPC_SSP1->DR;
}

What is length and where does it come from?
In that loop bufferpos is always zero, so you allways write to the same first position in the array. That means you allways overwrite the previous received byte and at the end there is only one byte in the arrray. Adding bufferpos++ can solve this.

[lpcware]

Content originally posted in LPCWare by qinnoNxp on Tue Dec 02 02:03:01 MST 2014
Hello,

my code for configuration:

SPIval[interface] = LPC_SSP1;
// Power
LPC_SYSCON->PRESETCTRL = (LPC_SYSCON->PRESETCTRL & 0x00000007) | (1UL << 2);
LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 18);
LPC_SYSCON->SSP1CLKDIV = 0x01;
// IOCON
HL_Iocon_SetPinMux(1, 22, IOCON_MODE_INACT, IOCON_FUNC2);
HL_Iocon_SetPinMux(1, 21, IOCON_MODE_INACT, IOCON_FUNC2);
HL_Iocon_SetPinMux(1, 20, IOCON_MODE_INACT, IOCON_FUNC2);
HL_Iocon_SetPinMux(1, 19, IOCON_MODE_INACT, IOCON_FUNC2);
SPIval[interface]->CR0 =  0x0107;
SPIval[interface]->CR1 = 4;
SPIval[interface]->CPSR = 0x30;
SPIval[interface]->IMSC = 0x07;
SPIval[interface]->CR1 |= 2;
NVIC_SetPriority(SSP1_IRQn,0);
NVIC_EnableIRQ(SSP1_IRQn);

Code for ISR:

BYTE buffer[256];
BYTE bufferpos=0;
void SSP1_IRQHandler(void)
{
       while((LPC_SSP1->SR & (1 << 2)) && bufferpos < length-1)
{
        buffer[bufferpos] = (BYTE)LPC_SSP1->DR;
        }

LPC_SSP1->ICR = (1UL<<0);   // Clear SSP0 "frame was received when RxFIFO was full" interrupt flag
LPC_SSP1->ICR = (1UL<<1);   // Clear SSP0 "Rx FIFO was not empty and has not been read for a timeout period" interrupt flag
}

I hope this will help me. Do you have an SSP Interface running as SPI and Slave?

Thanks and best regards.

[lpcware]

Content originally posted in LPCWare by 1234567890 on Mon Dec 01 12:26:17 MST 2014
The related code would improve your chances dramatically...