Content originally posted in LPCWare by rocketdawg on Thu Oct 01 06:50:06 MST 2015
Quote: rogerwilson
Hi,
The ISR seems to be run once per bit. I'm confused and wondered if there was any helpful notes somewhere.
Rog.
No, it cannot do that. This part has a FIFO and table of section 14.6.6/7 of UM10398 refers to the conditions upon which an interrupt may occur. Once per bit is not one of them. Section 14.7 explains the functional description. LPCOpen does abstract away much of the hardware specifics, but if one needs to know, then the User Manual is your reference.