Hi,
I have an SPI setup in the FLEXCOMM8 of LPC55s69 board. Its setup to be CPOL=0 and CPHA=0. I would expect the SCLK to return to 0 after each packet. However when scoping this, the observed behaviour is the opposite.
Is there a something that I can change to reverse this behaviour, as the chip i am interfacing with is getting erroneous data
Thanks
Hi Alice,
I am not using the MCUXpressoIDE, instead, I am using CLion, and in that case, I am not able to view the registers using PyOCD. I had raised a community post on it and was basically asked to use the MCUXpressoIDE. So i can not confirm it using register view, however using the confid tools, i am setting the CPOL to 0 and seeing the same in pheripherals.c
const spi_master_config_t FLEXCOMM8_config = {
.enableLoopback = false,
.enableMaster = true,
.polarity = kSPI_ClockPolarityActiveHigh,
.phase = kSPI_ClockPhaseFirstEdge,
.direction = kSPI_MsbFirst,
.baudRate_Bps = 1000000UL,
.dataWidth = kSPI_Data8Bits,
.sselNum = kSPI_Ssel0,
.sselPol = kSPI_SpolActiveAllLow,
.txWatermark = kSPI_TxFifo0,
.rxWatermark = kSPI_RxFifo1,
.delayConfig = {
.preDelay = 0U,
.postDelay = 0U,
.frameDelay = 0U,
.transferDelay = 0U
}
};
static void FLEXCOMM8_init(void) {
/* Initialization function */
SPI_MasterInit(FLEXCOMM8_PERIPHERAL, &FLEXCOMM8_config, FLEXCOMM8_CLOCK_SOURCE);
}
I had used a sample program similar to the SPI example and found the same behaviour
Now if i change the CPOL to 1, the behavior is as required. SPI clock and MOSI outputs default to low. This means that i cannot use CPOL=0 for interfacing with the system I am using. Is there any way to reverse this behaviour for CPOL=0?
Regards,
Joseph
Hello,
I use the SDK demo "lpcxpresso55s69_spi_interrupt_b2b_transfer_master"test the on my side, there is no problem.
BR
Alice
Hello ,
Could you please confirm SPI configuration register set CPOL to 0 correctly, can using IDE register view.
And how about use the SPI example under SDK to test.
BR
Alice