SGPIO with external clock and 1-bit input

[lpcware]

Content originally posted in LPCWare by rnunes on Thu Jul 16 07:43:42 MST 2015
I'm trying to implement a 1 bit "slave" device, with clock on SGPIO9 (pin 1.2) and using SGPIO3 (pin 1.16 - slice J0) as input, but I can't trigger anything.

Here's the code (I have a LPC4337):

#define SGPIO_SLICE (10) // Slice J
#define CMD_SGPIO_PIN (3)


    // Initialize the SGPIO interrupt (shared by shift/capture/match/input)
     NVIC_DisableIRQ(SGPIO_INT_IRQn);

     // clear interrupt status and wait for it to clear
     LPC_SGPIO->CTR_STATUS_1 = 0xffff;
     while(LPC_SGPIO->STATUS_1 & 0xffff);
     LPC_SGPIO->CTR_STATUS_2 = 0xffff;
     while(LPC_SGPIO->STATUS_2 & 0xffff);
     LPC_SGPIO->CTR_STATUS_3 = 0xffff;
     while(LPC_SGPIO->STATUS_3 & 0xffff);

     // disable all SGPIO interrupts
     LPC_SGPIO->CLR_EN_1 = 0xffff;
     while(LPC_SGPIO->ENABLE_1 & 0xffff);
     LPC_SGPIO->CLR_EN_2 = 0xffff;
     while(LPC_SGPIO->ENABLE_2 & 0xffff);
     LPC_SGPIO->CLR_EN_3 = 0xffff;
     while(LPC_SGPIO->ENABLE_3 & 0xffff);

     NVIC_EnableIRQ(SGPIO_INT_IRQn);

LPC_SGPIO->CTRL_ENABLED = 0; // disable all counters

// Configure pins
/// See Table 187. Pin multiplexing
Chip_SCU_PinMuxSet(1, 2, SCU_MODE_FUNC3 | SCU_PINIO_FAST);
Chip_SCU_PinMuxSet(1, 16, SCU_MODE_FUNC2 | SCU_PINIO_FAST);

//Connect SGPIO clock to Main_PLL
Chip_Clock_SetBaseClock(CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false);

LPC_SGPIO->OUT_MUX_CFG[CMD_SGPIO_PIN] = 0;

LPC_SGPIO->SGPIO_MUX_CFG[SGPIO_SLICE] =
1 << 0 |    // EXT_CLK_ENABLE
1 << 1 |    // CLK_SRC SGPIO9
3 << 5 |    // Qualifier mode : external clock
1 << 7;     // Qualifier pin: SGPIO9

LPC_SGPIO->SLICE_MUX_CFG[SGPIO_SLICE] =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(1L << 2) | // CLKGEN_MODE = 1 (use external clock)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0);  // MATCH_MODE = 0 (do not match data)

LPC_SGPIO->POS[SGPIO_SLICE] = (32UL-1) | (32UL-1)<<8; //Reload value for POS (32)

LPC_SGPIO->REG[SGPIO_SLICE] = 0x55555555; // Primary output data register
LPC_SGPIO->REG_SS[SGPIO_SLICE] = 0x55555555; // Shadow output data register

LPC_SGPIO-> GPIO_OUTREG = 0x00; // all pins input
LPC_SGPIO -> SET_EN_1 = 1 << SGPIO_SLICE;
LPC_SGPIO-> CTR_STATUS_1 = 0xFFFF;

LPC_SGPIO->CTRL_ENABLED = (1 << SGPIO_SLICE);
LPC_SGPIO->CTRL_DISABLED = ~( 1 << SGPIO_SLICE);

After that I try to use it with this code:

if(LPC_SGPIO->STATUS_1 & (1 << SGPIO_SLICE))
                {
                    bits = 32;
                    *ptr++ = LPC_SGPIO->REG[SGPIO_SLICE];

                    LPC_SGPIO -> CTR_STATUS_1 = 1 << SGPIO_SLICE;

                    while( ! (LPC_SGPIO->STATUS_1 & (1 << SGPIO_SLICE)));
                }

But STATUS_1 it's always 0, and I can see the data correctly in oscilloscope. Am I missing something?

[lpcware]

Content originally posted in LPCWare by DF9DQ on Sat Jul 18 12:36:56 MST 2015
In SGPIO_MUX_CFG you select SGPIO9 to be both the clock and the clock qualifier at the same time. That won't work.
I assume you do not want to qualify (= gate) the clock by any signal at all, but rather have all clock pulses shift the slice. In that case set the QUALIFIER_MODE field in SGPIO_MUX_CFG to 0 ("Enable"). The QUALIFIER_PIN_MODE and QUALIFIER_SLICE_MODE fields are don't care's then.