Content originally posted in LPCWare by mark03 on Fri Nov 23 12:48:41 MST 2012
Sorry, no, I don't actually have working hardware yet. The lack of an answer from NXP has me frozen back in the hardware design stage, because without clarity on SGPIO it's not clear which is the best way to interface my ADCs.
I was going to allow a month from Xianghui's post, but seeing as that expires next Tuesday... my best guess, unfortunately, is that he is having to reverse-engineer his company's own product. Having worked in a fairly dysfunctional tech organization myself, I know that this is a disturbingly common scenario :| He probably assumed it was possible, just like we did, and is now stuck, just like we are. This would also explain why the other NXP folks on the forum, like bavarian and wellsk, have studiously avoided making any comments in this thread: they don't know either, and are afraid to make a definitive statement for fear of being wrong.
At this point I have to put my project on the shelf and work on other things, until either NXP surprises us, or some other vendor releases a similarly performant M4 solution. It's really too bad.