SGPIO as SIMPLEX SLAVE SPI

[filippoguerzoni]

Hi,

on the M4 core of a board with LPC4357, I would like to implement SGPIO to get data at 5MHz as SIMPLEX SLAVE SPI (unidirectional stream, MISO not involved).

Here is my configuration:

SPI_CLK -> SGPIO11, SPI_CS -> SGPIO10 (qualifier), SPI_MOSI -> SGPIO12

I cannot make SGPIO slices work to get serial data in. Watching at LPC_SGPIO regs in debug (setting breakpoints) reveals that POS is never decremented. So the swap between REG and REG_SS does not happen and my SGPIO_handler IRS is never called.

I double cheked that external signals reach the MCU setting those pins as standard GPIOs in multiplexer. They are able to fire related GPIO_handler ISRs.

Maybe I'm missing something in SGPIO configuration. I tried both single (D slice) and concatenated slices (D+O slices) without success.

In the following my source code and attached the screenshot with input signals.

I would like to know what's happening.

Thank you

void setup_SGPIO_capture(void) {
    //Connect SGPIO clock to Main_PLL
    Chip_Clock_SetBaseClock(CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false);

    LPC_SGPIO->CLR_EN_0    = 0xffff;        // disable interrupting on clock
    LPC_SGPIO->CLR_EN_1    = 0xffff;        // disable interrupting on clock

    /* Disable all counters (should be in this state after reset but just make sure) */
    LPC_SGPIO->CTRL_ENABLED = 0;

    /* Set all pins as input */
    LPC_SGPIO->GPIO_OENREG = 0;

#define CLK_CAPTURE_MODE    (1<<1)        //CLOCK FALLING EDGE
#define CLKGEN_EXT            (1<<2)        //EXTERNAL CLOCK
#define INV_QUALIFIER        (1<<8)        //INVERTED QUALIFIER: CS ACTIVE WHEN LOW

#define EXT_CLK_ENABLE        1            //EXTERNAL PIN
#define CLK_SOURCE_PIN_MODE (3<<1)        //SGPIO11
#define QUALIFIER_MODE        (3<<5)        //EXTERNAL SGPIO
#define QUALIFIER_PIN_MODE    (2<<7)        //SGPIO10
#define CONCAT_ENABLE         (1<<11)        //ENABLE
#define CONCAT_ORDER        (1<<12)        //2 SLICES

    LPC_SGPIO->PRESET[sliceD] =
    LPC_SGPIO->PRESET[sliceO] = 0;

    LPC_SGPIO->COUNT[sliceD] =
    LPC_SGPIO->COUNT[sliceO] = 0;

    LPC_SGPIO->SLICE_MUX_CFG[sliceD] =
    LPC_SGPIO->SLICE_MUX_CFG[sliceO] = CLK_CAPTURE_MODE | CLKGEN_EXT | INV_QUALIFIER;

    LPC_SGPIO->SGPIO_MUX_CFG[sliceD] = EXT_CLK_ENABLE | CLK_SOURCE_PIN_MODE | QUALIFIER_MODE | QUALIFIER_PIN_MODE | CONCAT_ORDER;
    LPC_SGPIO->SGPIO_MUX_CFG[sliceO] = EXT_CLK_ENABLE | CLK_SOURCE_PIN_MODE | QUALIFIER_MODE | QUALIFIER_PIN_MODE | CONCAT_ENABLE | CONCAT_ORDER;

    LPC_SGPIO->POS[sliceD] =
    LPC_SGPIO->POS[sliceO] = ((0x20*2-1)<<8) | (0x20*2-1);    //POS & PRESET

    LPC_SGPIO->SET_EN_1 = 1<<sliceD;        //interrupt ONLY when slice 3/D switches data register

    /* Enable counter under test to start pixel stream generation */
    LPC_SGPIO->CTRL_ENABLED = (1<<sliceD) | (1<<sliceO);
}

int main(void)
{
    // Disable interrupts
    __asm volatile ("cpsid i");
    // equivalent to CMSIS '__disable_irq()' function

    setupHardware();

    /* Initialize the IPC Queue */
    IPCEX_Init();

    NVIC_SetPriority(SGPIO_INT_IRQn,0);

    // Clear all pending interrupts in the NVIC
    volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
    unsigned int irqpendloop;
    for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
        *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
    }

    //Vector table relocated to ram32
    memcpy(SRAM_VECTOR_TABLE, (uint32_t*)0x0, VECTOR_TABLE_SIZE_8);
    SCB->VTOR = (uint32_t)SRAM_VECTOR_TABLE;        //offset

    *(SRAM_VECTOR_TABLE + 47) = (uint32_t)SGPIO_IRQHandler;    //47=16+31

    // Reenable interrupts
    __asm volatile ("cpsie i");
    // equivalent to CMSIS '__enable_irq()' function

    //Setup SGPIO
    setup_SGPIO_capture();
    //NVIC_ClearPendingIRQ(SGPIO_INT_IRQn);
    NVIC_EnableIRQ(SGPIO_INT_IRQn);                    //Enable SGPIO Interrupt

    while (1) {
        MSleep(10);
    }

    return 0;
}

[filippoguerzoni · Accepted solution]

Code is fine, maybe it was a compilation issue.

Rebuilding everything fixed it.