SDRAM access problem(setup problem?)

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SDRAM access problem(setup problem?)

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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Mon Sep 09 23:23:24 MST 2013
Hi.
I'm testing now for Micron MT48LC32M16A2 on lpc1788 system,
It is a 16bit 512Mbit SDRAM.
No problem in the sequential write (increment pattern)of 64byte .
problem occurs at a 65byte data write.
But all data is abnormal by writing at 65 or later access.
Please comment if there is a factor to be considered.

Best regards.
  
<sdram>
  MT48LC32M16A2  8Meg×16×4banks
  Refresh Count 8k
  Row Addressing 8K(A0-A12)
  Bank Addressing 4(BA0,BA1)
  Column Addressing 1k(A0-A9)
<clock>
CCLK 120MHz
        EMC Clock 60MHz

<conection>
  lpc1788    sdram
  A[12:0]    A[12:0]
  A[14:13]   BA[1:0]
  D[15:0]    D[15:0]
  CAS        CAS#
  RAS        RAS#
  CS         CS#
  CLK        CLK
  CKE        CKE
  DQMH       DQMH
  DQML       DQML


<EMC & sdram setting>

EMC Dynamic Config0
// RBC
    EMCDynamicConfig0_bit.AML = 0x11;  // RBC 512Mb(32M×16),4banks row length= 13,column length = 10
// BRC
    EMCDynamicConfig0_bit.AML = 0x31;  // BRC 512Mb(32M×16),4banks row length= 13,column length = 10
                                       // AML 0x11 ->Config0 (0x0880)
                                       // AML 0x31 ->Config0 (0x1880)
Mode Register access

// RBC  row address length 13(A12-A0),4banks,column address length 10(A9-A0)
// 2(bank)+10(col length)+1(16bit device,A0 not used)=13 shift value
    Dummy = *((volatile unsigned short *)(0xA0000000 | (0x31<<13)));  // RBC


//BRC   4banks,row address length 13(A12-A0),column address length 10(A9-0)
// 10(col length)+1(16bit device,A0 not used) = 11 shift value
    Dummy = *((volatile unsigned short *)(0xA0000000 | (0x31<<11)));  // BRC





<Test Procedure>
1)Test Program Download
2)reset
3)run and break on program (initialize,SDRAM Write data test,break)
4)dump test area

<Test program>

void  sdramTest(int tno)
{ unsigned char cdt;
  unsigned short sdt;
  unsigned idt;
  unsigned char  *src_ucp,*dst_ucp;
  unsigned short *src_usp,*dst_usp,ss;
  unsigned int   *src_uip,*dst_uip,ii,cc;

 
  // sequential bytes write 
  dst_ucp = (unsigned char *)0xa0000000;
  for(cc=0;cc<64;cc++)                  // <--- write 64bytes
  {  
   *dst_ucp++ = cc;
  }


>> good case
>> sdram display the contents of the program at the terminated.
>> 0xa0000000 to 0xa0000000+64 has Increment data , so good

a0000000  00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
a0000010  10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
a0000020  20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
a0000030  30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
a0000040  02 41 02 43 02 43 02 43 02 43 02 43 02 43 02 43








  // sequential bytes write 
  dst_ucp = (unsigned char *)0xa0000000;
  for(cc=0;cc<64+1;cc++)                  // <--- write 64bytes
  {  
   *dst_ucp++ = cc;
  }
>> bad case
>> sdram display the contents of the program at the terminated.
>> 0xa0000000 to 0xa0000000+64 has not increment data , bad!!!!!!!!

a0000000  02 01 02 03 02 03 02 03 02 03 02 03 02 03 02 03
a0000010  12 11 12 13 12 13 12 13 12 13 12 13 12 13 12 13
a0000020  22 21 22 23 22 23 22 23 22 23 22 23 22 23 22 23
a0000030  32 31 32 33 32 33 32 33 32 33 32 33 32 33 32 33
a0000040  02 41 02 43 02 43 02 43 02 43 02 43 02 43 02 43





<initialize code>

void emc_configure_pin()
{

  IOCON_P2_16 = 0x21;    // EMC_CAS      (no pull-up/down) 
  IOCON_P2_17 = 0x21;    // EMC_RAS      (no pull-up/down)
  IOCON_P2_18 = 0x21;    // EMC_CLKOUT0  (no pull-up/down)
  IOCON_P2_20 = 0x21;    // EMC_DYCS0*   (no pull-up/down)
  IOCON_P2_24 = 0x21;    // EMC_CKEOUT0* (no pull-up/down)
  IOCON_P2_28 = 0x21;    // EMC_DQMOUT0  (no pull-up/down)
  IOCON_P2_29 = 0x21;    // EMC_DQMOUT1  (no pull-up/down)
  IOCON_P3_00 = 0x21;    // EMC_D[ 0]    (no pull-up/down)
  IOCON_P3_01 = 0x21;    // EMC_D[ 1]    (no pull-up/down)
  IOCON_P3_02 = 0x21;    // EMC_D[ 2]    (no pull-up/down)
  IOCON_P3_03 = 0x21;    // EMC_D[ 3]    (no pull-up/down)
  IOCON_P3_04 = 0x21;    // EMC_D[ 4]    (no pull-up/down)
  IOCON_P3_05 = 0x21;    // EMC_D[ 5]    (no pull-up/down)
  IOCON_P3_06 = 0x21;    // EMC_D[ 6]    (no pull-up/down)
  IOCON_P3_07 = 0x21;    // EMC_D[ 7]    (no pull-up/down)
  IOCON_P3_08 = 0x21;    // EMC_D[ 8]    (no pull-up/down)
  IOCON_P3_09 = 0x21;    // EMC_D[ 9]    (no pull-up/down)
  IOCON_P3_10 = 0x21;    // EMC_D[10]    (no pull-up/down)
  IOCON_P3_11 = 0x21;    // EMC_D[11]    (no pull-up/down)
  IOCON_P3_12 = 0x21;    // EMC_D[12]    (no pull-up/down)
  IOCON_P3_13 = 0x21;    // EMC_D[13]    (no pull-up/down)
  IOCON_P3_14 = 0x21;    // EMC_D[14]    (no pull-up/down)
  IOCON_P3_15 = 0x21;    // EMC_D[15]    (no pull-up/down)

  IOCON_P4_00 = 0x21;    // EMC_A[ 0]    (no pull-up/down)
  IOCON_P4_01 = 0x21;    // EMC_A[ 1]    (no pull-up/down)
  IOCON_P4_02 = 0x21;    // EMC_A[ 2]    (no pull-up/down)
  IOCON_P4_03 = 0x21;    // EMC_A[ 3]    (no pull-up/down)
  IOCON_P4_04 = 0x21;    // EMC_A[ 4]    (no pull-up/down)
  IOCON_P4_05 = 0x21;    // EMC_A[ 5]    (no pull-up/down)
  IOCON_P4_06 = 0x21;    // EMC_A[ 6]    (no pull-up/down)
  IOCON_P4_07 = 0x21;    // EMC_A[ 7]    (no pull-up/down)
  IOCON_P4_08 = 0x21;    // EMC_A[ 8]    (no pull-up/down)
  IOCON_P4_09 = 0x21;    // EMC_A[ 9]    (no pull-up/down)
  IOCON_P4_10 = 0x21;    // EMC_A[10]    (no pull-up/down)
  IOCON_P4_11 = 0x21;    // EMC_A[11]    (no pull-up/down)
  IOCON_P4_12 = 0x21;    // EMC_A[12]    (no pull-up/down)
  IOCON_P4_13 = 0x21;    // BA0 EMC_A[13]  (no pull-up/down)
  IOCON_P4_14 = 0x21;    // BA1 EMC_A[14]  (no pull-up/down)

  IOCON_P4_25 = 0x21;    // EMC_WE*      (no pull-up/down)
}


void emc_init()
{
    int i;
   
    volatile unsigned long Dummy;
    if(!(PCONP_bit.PCEMC)){
        PCONP_bit.PCEMC = 0x01;//電源、CLKの供給
    }
    emc_configure_pin();

   
    EMCCLKSEL_bit.EMCDIV = 1; // 120MHHz/1+(1)= 60MHz emcclk
   
    EMCDynamicConfig0_bit.B   = 0;  // Buffer disable
  
    EMCControl = 0; //disable
   
    for(Dummy = 0; Dummy<100000;Dummy++);
   
    //EMCStaticExtendedWait = 128;  // ?
   
    //EMCレジスタ設定   
    EMCDLYCTL_bit.CMDDLY = 31; //31;  // 7.75ns
    EMCDLYCTL_bit.FBCLKDLY = 31; //31;  // 7.75ns
    EMCDLYCTL_bit.CLKOUT0DLY = 31; //31;  // 7.75ns

    EMCControl = 1;//EMC enable
    
    EMCDynamicReadConfig = 1; //3; //2; //1;      // Clock out delayed strategy,using CLKOUT

    EMCDynamicRasCas0_bit.RAS = 3; //3; //2; RAS delay (CCLK)
    EMCDynamicRasCas0_bit.CAS = 3; //3; //2;
   
    EMCDynamictRP =  2;        //20nS 20nS*60MHz = 1.2 -> 2 
    EMCDynamictRAS = 3; //44nS  44nS*60MHz = 2.64 -> 3
    EMCDynamictSREX = 5; // 75nS 75nS*60MHz = 4.5 -> 5
    EMCDynamictAPR  = 5; // 5tCK?
    EMCDynamictDAL  = 5; // 6;          // 5tCK
    EMCDynamictWR   = 2; // 1CLK+7.5nS = 24nS -> 2tCK(33nS)
    EMCDynamictRC   = 4; // 66nS * 60MHz = 3.96 -> 4
    EMCDynamictRFC  = 4; // 4;          // 66nS * 60MHz = 3.96 -> 4
    EMCDynamictXSR  = 5; //8         // 75nS * 60MHz = 4.5 -> 5
    EMCDynamictRRD  = 15;         // 15tCK
    EMCDynamictMRD  = 2;          // 2tCK
   
    EMCDynamicConfig0_bit.MD = 0; // device is SDRAM
//  EMCDynamicConfig0_bit.AML = 0x11;  // RBC 512Mb(32M×16),4banks row length= 13,column length = 10
    EMCDynamicConfig0_bit.AML = 0x31;  // BRC 512Mb(32M×16),4banks row length= 13,column length = 10
                                       // AML 0x11 ->Config0 (0x0880)
                                       // AML 0x31 ->Config0 (0x1880)

    EMCDynamicConfig0_bit.B  = 0; // Buffer disable
    EMCDynamicConfig0_bit.P = 0;  // Writes not protect
      
// issue SDRAM NOP Command
    EMCDynamicControl = 0x00000183;
   for(volatile unsigned int kk = 2500; kk;kk--);
    

// issue SDRAM PRECHARGE Command
    EMCDynamicControl_bit.I   = 2;  // SDRAM PRECHARGE ALL command
    EMCDynamicRefresh = 1;
    for(volatile unsigned int kk = 2000; kk;kk--);  // > 128clk
    EMCDynamicRefresh = 27;        // (7.8uS*60MHz)/16 =29.25
   

// issue SDRAM MODE Command
    EMCDynamicControl_bit.I   = 1;  // SDRAM MODE command
   
//  Dummy = *((volatile unsigned short *)(0xA0000000 | (0x21<<13)));  // RBC
    Dummy = *((volatile unsigned short *)(0xA0000000 | (0x31<<11)));  // BRC
    EMCDynamicControl  = 0;  // SDRAM Normal Operation    
    EMCDynamicConfig0_bit.B   = 1;  // Buffer enable
}

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NXP Employee
NXP Employee
Content originally posted in LPCWare by studyembedded on Tue Oct 01 23:25:12 MST 2013
Thanks my friend...i appreciate your efforts!
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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Tue Oct 01 19:01:51 MST 2013
Hi studyembedded  and everyone!

I agree for your comment.
my last code refer to attach files ,
It is using CAS Latency=3 RAS-CAS Latency=3...... ,
You must have check the performance  with each parameters.

using environment  : IAR
using resource:
LPC1788 CCLK 120MHz
EMCCLK 60MHz
SDRAM  Micron MT48LC32M16A2(8Meg×16×4banks)×1
(RBC mode)

Best Regards.

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NXP Employee
NXP Employee
Content originally posted in LPCWare by studyembedded on Tue Oct 01 03:30:00 MST 2013
Hi Hiro,
It nice that you manage to solve it, It would a great help to other people if you can share the code here. This is how the forums are run, my humble request to you is, Please share working code for the help of this community...thanks!
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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Mon Sep 30 22:48:26 MST 2013
Hi iamzhangyong and Everyone

My problem was solved.
There seemed to implementation issues on the cause.
Problem was solved where it is equipped with the same SDRAM remove the SDRAM, was soldered.
Of course, from you about the SDRAM initialization Comment was very important.
Thanks!!!

Best Regards.

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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Mon Sep 23 20:53:53 MST 2013
Hi iamzhangyong!

Thanks for your comment!
I have confirmed the behavior of LPC2478STK EVM at your help.
Burst length of SDRAM parameters or would not come only involved in performance?
Required tuning of burst length and Why?


Good, work properly below
>> 0x33<<12.

Not good, it does not work properly below
>> 0x32<<12.


Best Regards.
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NXP Employee
NXP Employee
Content originally posted in LPCWare by iamzhangyong on Thu Sep 19 07:30:03 MST 2013
Hi hiroto
  The difference of setting between 32bit and 16bit shows below
  1)EMCDYNAMICCFG,This register you have modified for 16bit sdram.
  2)SDRAM initalize command.
    volatile unsigned long Dummy = *(volatile unsigned short *)((Int32U)&SDRAM_BASE_ADDR + (0x32UL << (13)));This statement is in your software.I think it should be *(volatile unsigned int *)(...) to set 32bit SDRAM and *(volatile unsigned short *)(...) to set 16bit SDRAM.If the setting of 32bit SDRAM is 0x32 << 13,the 16bit may be 0x33<<12.The problem you got likes the data doesn't write to sdram,it just in the sdram buffer.When the data number you write pass 64 it can cause a burst write to sdram.The initalization of SDRAM doesn't work.So the data will be error.The EMCDLYCTL is a very important register to SDRAM controller.You should check up the register carefully.

iamzhangyong
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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Wed Sep 18 21:19:26 MST 2013
Hi iamzhangyong! and everyone!

I showing a result of the sample program on LPC2478 evaluation board (IAR LPC2478stk).
LPC2478 evaluation board is used by the mapping of 32bit SDRAM.
It's used  two device(16bit SDRAM,K4S561632J-UC75x2) in fact.
I confirmed good working  in this 32bit environment.
However,  I  confirmed  the previous and similar  problem at  16bit configuration.

I following the test results of three.
What's missing?
How to use to a (single) SDRAM(16bit) ?


case 1: Expected  with EMCDYNAMICCONFIG0 = 0x4680(32bit)
case 2: Unexpeced with EMCDYNAMICCONFIG0 = 0x0680(16bit)
case 3: Expected if access length is short with EMCDYNAMICCONFIG0 = 0x0680(16bit)


Best Regards.
Hiroto



I describe in more detail below.
==========================================================
void SDRAM_Init (void)
{
  // Assign pins to SDRAM controller
  PINSEL5 &= BIN32(00000000,11111100,11111100,11000000);
  PINSEL5 |= BIN32(01010101,00000001,00000001,00010101);
  PINMODE5&= BIN32(00000000,11111100,11111100,11000000);
  PINMODE5|= BIN32(10101010,00000010,00000010,00101010);
  PINSEL6  = BIN32(01010101,01010101,01010101,01010101);
  PINMODE6 = BIN32(10101010,10101010,10101010,10101010);
  PINSEL7  = BIN32(01010101,01010101,01010101,01010101);
  PINMODE7 = BIN32(10101010,10101010,10101010,10101010);
  PINSEL8 &= BIN32(11000000,00000000,00000000,00000000);
  PINSEL8 |= BIN32(00010101,01010101,01010101,01010101);
  PINMODE8&= BIN32(11000000,00000000,00000000,00000000);
  PINMODE8|= BIN32(00101010,10101010,10101010,10101010);
  PINSEL9 &= BIN32(11111111,11110011,11111111,11111111);
  PINSEL9 |= BIN32(00000000,00000100,00000000,00000000);
  PINMODE9&= BIN32(11111111,11110011,11111111,11111111);
  PINMODE9|= BIN32(00000000,00001000,00000000,00000000);

  // Init SDRAM controller
  // Enable EMC clock
  PCONP_bit.PCEMC = 1;
  EMCCONTROL      = 1;         // enable EMC
  EMCDINAMICRDCFG = 1;
  EMCDYNAMICRASCAS0_bit.CAS = 3;
  EMCDYNAMICRASCAS0_bit.RAS = 3;
  EMCDYNAMICRP = P2C(SDRAM_TRP);    // SDRAM_TRP(20nS)
  EMCDYNAMICRAS = P2C(SDRAM_TRAS);  // SDRAM_TRAS(45nS)
  EMCDYNAMICSREX = P2C(SDRAM_TXSR); // SDRAM_TXSR(67nS)
  EMCDYNAMICAPR = SDRAM_TAPR;       // SDRAM_TAPR(1)
  EMCDYNAMICDAL = SDRAM_TDAL+P2C(SDRAM_TRP); // SDRAM_TDAL(3)+
  EMCDYNAMICWR = SDRAM_TWR;         // SDRAM_TWR(3)
  EMCDYNAMICRC = P2C(SDRAM_TRC);    // SDRAM_TRC(65nS)
  EMCDYNAMICRFC = P2C(SDRAM_TRFC);  // SDRAM_TRFC(66nS)
  EMCDYNAMICXSR = P2C(SDRAM_TXSR);  // SDRAM_TXSR(67nS)
  EMCDYNAMICRRD = P2C(SDRAM_TRRD);  // SDRAM_TRRD(15nS)
  EMCDYNAMICMRD = SDRAM_TMRD;       // SDRAM_TMRD(3)
  //EMCDYNAMICCFG0 = 0x0000680;        // 13 row, 9 - col, SDRAM
  EMCDYNAMICCFG0 = 0x0004680;
  // JEDEC General SDRAM Initialization Sequence
  // DELAY to allow power and clocks to stabilize ~100 us
  // NOP
  EMCDINAMICCTRL = 0x0183;
  for(volatile Int32U i = 200*30; i;i--);
  // PALL
  EMCDINAMICCTRL_bit.I = 2;
  EMCDINAMICRFR = 1;
  for(volatile Int32U i= 128; i; --i); // > 128 clk
  EMCDINAMICRFR = P2C(SDRAM_REFRESH) >> 4;
  // COMM
  EMCDINAMICCTRL_bit.I = 1;
  // Burst 4, Sequential, CAS-3
  volatile unsigned long Dummy = *(volatile unsigned short *)
                                  ((Int32U)&SDRAM_BASE_ADDR + (0x32UL << (13)));
  // NORM
  EMCDINAMICCTRL = 0x0000;
  EMCDYNAMICCFG0_bit.B = 1;
  for(volatile Int32U i = 10000; i;i--);
}


void  sdramtest()
{
      unsigned char *ptr;
      int           dt = 1;
      ptr = (unsigned char *)(0xa0000000);
      for(int cnt=0;cnt<256;cnt++){          // 256bytes
          *ptr++ = cnt;
          
      }
}


---------------------------------------------------------------
case 1

Memory display after program execution(sdramtest) (32bit SDRAM mapping)

  //EMCDYNAMICCFG0 = 0x0000680;        // 13 row, 9 - col, SDRAM
  EMCDYNAMICCFG0 = 0x0004680;

0xa0000000  00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f <Expected
0xa0000010  10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f <Expected
0xa0000020  20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f <Expected
0xa0000030  30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f <Expected
0xa0000040  40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f <Expected
0xa0000050  50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f <Expected
0xa0000060  60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f <Expected
0xa0000070  70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f <Expected
0xa0000080  80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f <Expected
0xa0000090  90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f <Expected
0xa00000a0  a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af <Expected
0xa00000b0  b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf <Expected
0xa00000c0  c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf <Expected
0xa00000d0  d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df <Expected
0xa00000e0  e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef <Expected
0xa00000f0  f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff <Expected
0xa0000100  80 81 ef fe 82 83 ff ff 84 85 ff ff 86 87 bf fb


---------------------------------------------------------------
case 2
Memory display after program execution(sdramtest) (16bit SDRAM mapping)


  EMCDYNAMICCFG0 = 0x0000680;        // 13 row, 9 - col, SDRAM
  //EMCDYNAMICCFG0 = 0x0004680;

0xa0000000  04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 <Unexpected
0xa0000010  14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 10 11 12 13 <Unexpected
0xa0000020  24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 20 21 22 23 <Unexpected
0xa0000030  34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 30 31 32 33 <Unexpected
0xa0000040  40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f <Unexpected
0xa0000050  50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f <Unexpected
0xa0000060  60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f <Unexpected
0xa0000070  70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f <Unexpected
0xa0000080  80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f <Unexpected
0xa0000090  90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f <Unexpected
0xa00000a0  a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af <Unexpected
0xa00000b0  b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf <Unexpected
0xa00000c0  c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf c0 c1 c2 c3 <Unexpected
0xa00000d0  d4 d5 d6 d7 d8 d9 da db dc dd de df d0 d1 d2 d3 <Unexpected
0xa00000e0  e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef e0 e1 e2 e3 <Unexpected
0xa00000f0  f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff f0 f1 f2 f3 <Unexpected
0xa0000100  ff ff ff f7 df ff 7f 9f fd fe ff ff df ff 7f ff <


---------------------------------------------------------------
case 3

void  sdramtest()
{
      unsigned char *ptr;
      int           dt = 1;
      ptr = (unsigned char *)(0xa0000000);
      for(int cnt=0;cnt<64;cnt++){      // 64bytes
          *ptr++ = cnt;
          
      }
}

    -----------------------------------------------------------

Memory display after program execution(sdramtest) (16bit SDRAM mapping)

  EMCDYNAMICCFG0 = 0x0000680;        // 13 row, 9 - col, SDRAM
  //EMCDYNAMICCFG0 = 0x0004680;

0xa0000000  00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f <Expected
0xa0000010  10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f <Expected
0xa0000020  20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f <Expected
0xa0000030  30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f <Expected
0xa0000040  44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 40 41 42 43




-----------------------------------------------------
LPC2478-STK connection

   SDRAM#1,#2 K4S561632J-UC75(16Mx16)x2
   Row A0-A12
   Col A0-A8
  
  

LPC2478     SDRAM#1      SDRAM#2
---------+-------------+-------------
A0     <-----> A0    <-----> A0
A1     <-----> A1    <-----> A1
A2     <-----> A2    <-----> A2
A3     <-----> A3    <-----> A3
A4     <-----> A4    <-----> A4
A5     <-----> A5    <-----> A5
A6     <-----> A6    <-----> A6
A7     <-----> A7    <-----> A7
A8     <-----> A8    <-----> A8
A9     <-----> A9    <-----> A9
A10    <-----> A10   <-----> A10
A11    <-----> A11   <-----> A11
A12    <-----> A12   <-----> A12
A13    <-----> BA0   <-----> BA0
A14    <-----> BA1   <-----> BA1
SDCLK  <-----> CLK   <-----> CLK
SDCLKEN<-----> CKE   <-----> CKE
SDCS   <-----> CS    <-----> CS
SDWEN  <-----> WE    <-----> WE
CASN   <-----> CAS   <-----> CAS
RASN   <-----> RAS   <-----> RAS
DQMN0  <-----> DQML
DQMN1  <-----> DQMH
DQMN2  <------------------->DQML
DQMN3  <------------------->DQMH
D0     <-----> D0
D1     <-----> D1
D2     <-----> D2
D3     <-----> D3
D4     <-----> D4
D5     <-----> D5
D6     <-----> D6
D7     <-----> D7
D8     <-----> D8
D9     <-----> D9
D10    <-----> D10
D11    <-----> D11
D12    <-----> D12
D13    <-----> D13
D14    <-----> D14
D15    <-----> D15
D16    <------------------> D0
D17    <------------------> D1
D18    <------------------> D2
D19    <------------------> D3
D20    <------------------> D4
D21    <------------------> D5
D22    <------------------> D6
D23    <------------------> D7
D24    <------------------> D8
D25    <------------------> D9
D26    <------------------> D10
D27    <------------------> D11
D28    <------------------> D12
D29    <------------------> D13
D30    <------------------> D14
D31    <------------------> D15



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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Wed Sep 18 18:39:49 MST 2013

Hi iamzhangyong!

I tried to change burst length a variety of SDRAM initialization parameter.
It does not work properly in both. Unfortunately.

hiroto
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NXP Employee
NXP Employee
Content originally posted in LPCWare by iamzhangyong on Wed Sep 18 09:07:25 MST 2013
Hi hiroto!
  According to the datasheet the Buffer must be enable on sdram running,so I set the enable bit of the dynamicconfig register.
  Dummy = *((volatile unsigned short *)(0xA0000000 | (0x31<<13))); // RBC
  You set the SDRAM Burst Length to 2,but LPC1788 support Burst Length to be 8 at 16bit or 4 at 32bit.It is the problem?You can try   Dummy = *((volatile unsigned short *)(0xA0000000 | (0x33<<13))); // RBC .This statement will initalise the sdram's burst length to 8

  I hope it is helpful.

iamzhangyong
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NXP Employee
NXP Employee
Content originally posted in LPCWare by hiroto on Tue Sep 17 00:28:40 MST 2013
Hi iamzhangyong

Thank you for your comment.
However, it seems different from the problems you are encountering.
the circuit I designed is a simple connection.
(Or that of the LPC internal hardware?)
I also when debugging, you access the SDRAM space with disable Buffer of EMC
was  the fault exception occurs .
Does you set enable  the Buffer?(EMCDynamicConfig0_bit.B = 1)

Best Regards.
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NXP Employee
NXP Employee
Content originally posted in LPCWare by iamzhangyong on Fri Sep 13 09:04:13 MST 2013
Dose it a hardware problem ? I design a board with LPC1788 and HY57V281620,it has problems random.The arm went to hardfault_handler.
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