SDK - how to config ADC input pin/channel ?

[frank_m]

I am looking for an example to proper initialize an input channel for the ADC (LPC54628).

The usual way is to enable the appropriate GPIO pin, and assign the proper function (analog mode).

All of the SDK examples use the internal temperature sensor - and cleverly circumvent a proper how-to.

Can any one show me the proper SDK calls, and sequence ?

I want to use ADC0 and ADC0IN4..6, but an example for one pin/channel would suffice.

Thanks.

[Alice_Yang]

Hello frank meyer,

Please refer to the below application, it use channel 4, download from:

https://www.nxp.com/docs/en/application-note/TN00017.zip 

It includes application notes and source code, this project support MCUXpresso IDE, IAR and KEIL.

Have a great day,
TIC

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[frank_m]

Thinking about it, I finally came to realize the SDK is not a library designed as such to work with a certain MCU.

Instead, it is auto-generated from a config tool, using a loose set of peripheral drivers (fsl_xxx.c/.h), device-specific files, and middleware utilitites.

I'm probably supposed to use the ConfigTool in the MCUXpresso IDE instead.

I'm going to look into it.

[Alice_Yang]

Hi Frank,

Yes, I also  recommend you use MCUXpresso Config tool.

BR

Alice

[frank_m]

Since it belongs to the topic, I'd like to ask a follow-up question.

I have configured 3 channels with a sequenceA interrupt, which basically works.

However, my interrupt handler routine proved incorrect.

Section 44.6.5, table 1032 (page 1049) of UM10912 says:
SEQA_GDAT register, Bit 31: DATA VALID
This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read.
This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).

Thus, I checked for the DATA_VALID bit of said register, which was never set.

Consequently, the code never cleared any flags, and the interrupt fired continuously.

I then checked the SDK example code (from TN00017), and the ADC interrupt handler code there goes for the ADC.FLAGS register instead.

Again quoting the relevant part of the user manual,Section 44.6.11, table 1041 (page 1078):
Bit 28: SEQA_INT

Sequence A interrupt/DMA trigger.
If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read.
If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.

The MODE bit of SEQA_CTRL is set (as I configured).

I basically copied this code (check for FLAGS.SEQA_INT flag instead of SEQA_GDAT.DATA_VALID), which works as expected.

However, I cannot find any indication in the UM why the DATA_VALID bit in SEQA_GDAT is not set at the same time. Do I miss something ?

[Alice_Yang]

Hello frank,

From the below information of UM, DATAVALID will be cleared whenever it is read, and the SEQA_INT

mirror the DATAVALID bit, meaning read it, so it is 0.

And in almost case, please use flags to check whether finish conversion.

BR

Alice

[frank_m]

From the below information of UM, DATAVALID will be cleared whenever it is read, and the SEQA_INT

mirror the DATAVALID bit, meaning read it, so it is 0.

I have read it, and understood (at least, I think). And I'm aware of debugger intrusiveness in this case.

My first line in the ADC interrupt handler translated to something like :

if (ADC0->SEQ_GDAT[0] & 0x80000000) { ...

This condition was never fulfilled. I didn't have a peripheral register debug view open at that time, and this was supposedly the first (read) access.

Anyway, the FLAG register based code works.

Not to be too nitpicking, but albeit the UM differs between SEQA_GDAT and SEQB_GDAT, the SDK code (fsl_adc.*) knows only SEQ_GDAT[2].

[Alice_Yang]

Hello frank,

So the SDK code is an important supplement .:smileywink:

[frank_m]

So the SDK code is an important supplement .

Understand and agree ... ;-)

[frank_m]

Thanks, that should work for me.

Albeit it is a bit convoluted - I expected the GPIO configuration in the ADC init context, but instead it is "hidden" in the one-for-all pin_mux module.