Content originally posted in LPCWare by ArriaLive on Thu Aug 28 09:03:38 MST 2014
MC, thank you for your response!
I am aware that the flash memory space is mirrored, and I get the same values when I peek at the memory locations. The M4MEMMAP is pointed to 0x80000000 which is at least fine for now. I can change it to 0x14000000, and have done that, but it makes no difference.
Here's the problem:
1 - I read and XIP from flash, and can validate it. I also read the SPIFI MEMCMD register to see what the value is.
2 - I send a reset (0x10) to STAT register, then wait for the reset to complete. At this point the memory at 0x14000000 is unreadable (expected).
3 - I immediately put SPIFI back in memory mode with the same value that was in the MEMCMD before.
That's it. After these simple steps, I can verify that SPIFI is in memory mode (MCINIT set to 1), I can peed at the memory at 0x14000000, but the content of the memory has completely changed--to 0s or all 0xCCCCCCCC.
My question is, where did my memory go? Is there some register somewhere in the processor that is cleared when I do the reset? What does the bootloader do to "set up" the SPIFI? Do I need to do that again after the reset? What are those steps?
Note that we are not using the boot pins in our design, but are using the boot_src in the OTP processor memory, currently set to 0b0010. This works quite well for normal booting on its own, but maybe doesn't work for SPIFI init?
Also, note that I have been able to get the SPIFI out of memory mode without using the reset (by simply sending a different CMD (MBR, RDSTR1, etc.). Following these commands, I can usually put SPIFI back into memory mode successfully. That is my work around for now, but it is contrary to the documentation.
Thanks,
EdA