Rock solid UART ISR for LPC1343?

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Rock solid UART ISR for LPC1343?

Contributor I

Trying to build a 'rock solid' uart Interrupt service routine ('UART_IRQHandler()') for LPC1343.
Should be able to synchronize to a running serial stream which has data packets separated by 100 msec gaps between them.
Some sentences in Manual UM10375 are not clear enough for me.

Example 1:
Uart IIR on page188: "The UART RLS set whenever any one of four error conditions occur..."
Referenced are OE, PE, FE and BI. What about RXFE? When RXFE will be set?

Example 2:
PE in U0LSR on page 194: "Time of parity error detection is dependent of U0FCR[0]: What does that mean?
Will I get PE when error char is loaded from RSR into FIFO? Or will I get PE if I read a char from the FIFO?

FE description is - at first sight - more exact: "A framing error is associated with the character at the top of the UART RBR FIFO". If FIFO is enabled, do we then have an 'array RBR[16]'?

Maybe one has solved such and may provide hints for handling LPC1343 in ISR?
Best regrards Juergen

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Contributor I

Lets say, FIFO Trigger level is set to 14 chars. 13 chars are in, no Interrupt trigger so far.
Now the 14th char comes in and has parity error.

Which U0IIR flags and which U0LSR flags will the interrupt handler get?

Best regards Juergen

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NXP TechSupport
NXP TechSupport

Hi Juergen Marquardt,

Thank you for your interest in NXP Semiconductor products and 
the opportunity to serve you.
To provide the fastest possible support I want to point you to a 
similar question which has been answered on our NXP community. 
Please refer to periph_uart_rb demo which is come from the lpcopen_2_05_keil_iar_nxp_lpcxpresso_1343
to view the details.

Have a great day,

Note: If this post answers your question, please click the Correct Answer button. Thank you!

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