Ramp up time requirement on VBAT_DCDC =1.8V of LPC55S1x

[JaehoonLee13]

Hello,

I recently noticed that the hardware design guideline document (AN13033) strongly requires the implementation of the ramp up time on VBAT_DCDC.

The minimum ramp up time (0 to 105dC range) on the datasheet is 0.5msec and the test condition was VBAT_DCDC=3.6V.

In our system, VBAT_DCDC is supplied with 1.8V. In this case, can I assume that the minimum ramp up time is 0.25msec (which is the half of 0.5msec)?

Additionally, the document warns about the ramp up time such that 

The device may not always start and may damage the device if the minimum rise time of the power supply ramp is 2.6 ms or faster for Tamb = -40 °C, and 0.5 ms or faster for Tamb = 0 °C to +105 °C.

Could you elaborate how this ramp up time violation could permanently damage the device? 

Best,

Jaehoon

[ZhangJennie]

Hello JaehoonLee13, 

The minimum specified VBAT_DCDC is 1.8V, which means that if it is supplied with 1.79V, it can't work normally. So I suggest you supply VBAT_DCDC with 1.9V for the reliability purpose.The voltage ramp-up characteristic approximates linearity but I suggest allowing some margin.
Based on above analysis, a minimum ramp-up time of 0.3ms should no issue.

Hope this helps,

Jun Zhang

[JaehoonLee13]

Thanks Jun for confirming the ramp up time requirement for 1.8V supply.

Could you also check what could be the possible failure mode of not following the ramp up time? How it could possibly damage the chip?

Also, Is this ramp up time required to implement the time delay between the Main IO supply and the VBAT_DCDC supply, when they are supplied by the same source? In other words, if this ramp up time is for ensuring the supplying the VDD first and then VBAT_DCDC with some time delay, I need to modifiy the system design accordingly, as my design is supplying both VDD and VBAT_DCDC with the single 1.8V supply rail.

[ZhangJennie]

Hi JaehoonLee13 

If not comply with the specified ramp-up time, it may result in unexpected issues, such as a failed Power-On Reset (POR), permanent chip damage, or other critical failures. Therefore, violating this requirement is strictly prohibited.

The ​core voltage must power up ​before or simultaneously with the I/O voltage, and it should stabilize earlier.

Hope this helps,

Jun Zhang