RTC on LPC54605

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RTC on LPC54605

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anadimartel
Contributor I

Hello,

Our LPC54605 PCB requires use of the RTC with external 32Khz oscillator and VBAT battery backup. In the LPC546 spec sheet and in 2018-2019 NXP Community posts on this subject, there seems to be a confusion regarding the necessity of connecting the battery to both VBAT and VDD OR only to VBAT for proper low-current RTC count.

1) Is connecting battery to VBAT only while VDD goes to 0V sufficient to retain RTC count with Ibat < 1uA as listed in the spec sheet (assuming the RESET pin is left floating)? To achieve this, is there any particular BOD code needed to enter deep-powerdown level before VDD disappears?

2) If on the other hand the battery must be connected to both VBAT and VDD for RTC count after disappearance of external supply, then some kind of circuit detecting this disappearance of external VDD is needed in order to trigger deep-powerdown level. Furthermore, at restoration of external supply some mechanism is needed to generate a reset pulse at RESET pin (since this is the only way to come out of deep-powerdown level), all the while leaving the RESET pin floating while in battery mode. Do you have examples of such circuit / code?

I wonder why such complications were introduced in the LPC546, while older processors such as LPC2300 had perfectly simple and functional VBAT/RTC implementations?

Thanks

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Q1)you confirm that case #1 is working. Is entering Deep-Powerdown mode through software command before VDD = 0V required to achieve Ibat = 340nA, or is Deep-Powerdown mode irrelevant once VDD = 0V and the uC stops? Your documentation is really not clear on this point (specifically section 19.4.3).

>>>>It does not matter whether you enter Deep-Powerdown mode before you VDD=0 or you let VDD to 0 directly, the Ibat result is the same.

 

Q2)In real-life PCB many pins of the uC are connected to circuit parts. Assuming the RESET pin is kept floating, will there be no leakage from any other pins leading to higher Ibat when VBAT is driven by the battery and VDD is off?

>>>>>>Assuming the RESET pin is kept floating, there will be no leakage from any other pins leading to higher Ibat when VBAT is driven by the battery and VDD is off. The Vbat is an independent power domain.

Hope it can help you

BR

XiangJun Rong

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anadimartel
Contributor I

Thanks,

OK you confirm that case #1 is working. Is entering Deep-Powerdown mode through software command before VDD = 0V required to achieve Ibat = 340nA, or is Deep-Powerdown mode irrelevant once VDD = 0V and the uC stops? Your documentation is really not clear on this point (specifically section 19.4.3).

In real-life PCB many pins of the uC are connected to circuit parts. Assuming the RESET pin is kept floating, will there be no leakage from any other pins leading to higher Ibat when VBAT is driven by the battery and VDD is off? 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Q1)you confirm that case #1 is working. Is entering Deep-Powerdown mode through software command before VDD = 0V required to achieve Ibat = 340nA, or is Deep-Powerdown mode irrelevant once VDD = 0V and the uC stops? Your documentation is really not clear on this point (specifically section 19.4.3).

>>>>It does not matter whether you enter Deep-Powerdown mode before you VDD=0 or you let VDD to 0 directly, the Ibat result is the same.

 

Q2)In real-life PCB many pins of the uC are connected to circuit parts. Assuming the RESET pin is kept floating, will there be no leakage from any other pins leading to higher Ibat when VBAT is driven by the battery and VDD is off?

>>>>>>Assuming the RESET pin is kept floating, there will be no leakage from any other pins leading to higher Ibat when VBAT is driven by the battery and VDD is off. The Vbat is an independent power domain.

Hope it can help you

BR

XiangJun Rong

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Q1) Is connecting battery to VBAT only while VDD goes to 0V sufficient to retain RTC count with Ibat < 1uA as listed in the spec sheet (assuming the RESET pin is left floating)? To achieve this, is there any particular BOD code needed to enter deep-powerdown level before VDD disappears?

>>>>The RTC and RTC oscillator circuit are driven by VBAT, the RTC will continue to count 1Hz tick if VBAT power supply exists ,even if VDD power supply voltage disappears. In the case, Ibat is less than 1uA, based on data sheet, typical is 340nA.

Q2) If on the other hand the battery must be connected to both VBAT and VDD for RTC count after disappearance of external supply, then some kind of circuit detecting this disappearance of external VDD is needed in order to trigger deep-powerdown level. Furthermore, at restoration of external supply some mechanism is needed to generate a reset pulse at RESET pin (since this is the only way to come out of deep-powerdown level), all the while leaving the RESET pin floating while in battery mode. Do you have examples of such circuit / code?

>>>>The RTC and related clock circuit are driven by only VBAT, you can use the battery to VBAT and use the other power to the VDD, in the case, you can initiailize the RTC. After initialization is over, the RTC run. In the case, even if VDD disappears, the RTC can continue to run.

Pls download SDK package:

https://mcuxpresso.nxp.com/en/welcome

 

 

https://community.nxp.com/t5/LPC-Microcontrollers/RTC-Operation-in-power-down-mode-in-LPC546xx-Micro...

Hope it can help you

BR

XiangJun Rong

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