RMII Mode

[lpcware]

Content originally posted in LPCWare by PhilYoung on Wed Apr 18 00:54:23 MST 2012
Has anybody tried to build the WebApp example for the Hitex board using RMII mode.
I've been trying to get hold of the Hitex board but they are on 30 day leadtime and no stock anywhere, so I'd appreciate if anybody has any experience with this.

It looks to me like there is a bug in the code but I can't verify this, seems that the PHY clocks are set to 25MHz internally using ClkDivA which does not make sense for RMII mode.

Any feedback would be really appreciated.

regards

Phil.

[lpcware]

Content originally posted in LPCWare by ashgupta28 on Tue Dec 09 01:49:52 MST 2014
I am also using custom board with LPC18xx with KSZ8863RLL. I am trying to read & write PHY registers. Actually I am using CLOCK MODE & MDIO SMII Mode (RMII mode) to access registers. I guess as per the MII format, only 5bit register address & 5 bit Phy address can be used.
I am using 25MHZ crystal populated at X1 & X2 at PHY switch.

BUT I AM GETTING GARBAGE VALUES WHILE READING THESE KSZ8863RLL REGISTERS

HERE ARE THE STEPS I AM FOLLOWING:-
1.Configure the LPC processor clock & enabled the RMII interface of LPC
2.Configure the PHY address PHY 1( this configuration helps to create the RMII frame format and adding the PHY address 0x01 in PHY address Bits[4:0]
3.As per our set up, LPC processor is receiving 50MHz reference clock.(Please correct me if I am wrong). So what settings need to be in done in LPC as per clock. I have selected CLK_M3_ETHERNET/102

4.After that I tried to read MII_PHYSID1(0x02) & MII_PHYSID2(0x03) with PHY address 0x01. It will return only 16bit data (should return 0x0022 & 0x1430) as per the format. But I receive only the garbage value. Also I tried to connect the LAN cable at port 1 & tried to read the MII_BMSR to check the LINK up or down but the value I am reading is 0x0000 every time. The LEDs & LINK LEDs blinks properly after connecting the cable but still I am getting 0x00 value.

if (lpc_mii_read(0x00, &tmp) != SUCCESS) {
return ERROR;
}

I have selected PHY address 1 & trying to read 0x00 register
lpc_read_read is actually configuring the packet as per the datasheet & sending to Micrel chip

[lpcware]

Content originally posted in LPCWare by PhilYoung on Fri Apr 27 01:06:51 MST 2012
I got a Hitex board now and got the RMII code working eventually ( there are bugs in the 2012-04-17 example code ), this works on Hitex but not on our board with the 1126 silicon so I'll assume it was a bug in that chip revision for now.

Regarding the Hitex RMII code, there is a bug in clock selection, it should just select the Tx clock as the phy Tx and Rx clocks as they need to be 50Mhz and synchronous to the PHY clock.
The second problem is the phy defaults to MII mode at power on with the strapping options, and the SW does not program the register to place it into RMII mode.
adding the line
#if !MII
  write_PHY (PHY_REG_RBR, 0x20); missing from the demo, puts the phy into RMII mode 1.2

#endif


immediately after the update of the BMCR register puts the PHY into RMII mode then the example works fine.

[lpcware]

Content originally posted in LPCWare by PhilYoung on Sat Apr 21 02:58:31 MST 2012
Thanks,
We never used RMII mode, on the Raptor-TC2 I used MII mode.
On our current board the parts are labelled
FalconM4
P6G566
ESD1126AX

but I don't have a specific errata for this revision, but I do know is the version which reports 3 Jtag interface ports.

I'm having a new board revision assembled at the moment so need to ensure this gets a later revision then I will test it.

Thanks for the pointer on the Phy, I'll look into it.

regards

Phil.

[lpcware]

Content originally posted in LPCWare by DPeters on Fri Apr 20 15:13:19 MST 2012
The LPC1850 Rev'-' has an errata for RMII not working.  My guess is that the engineering sample LPC4300 Rev 'TC2' had a similar EMAC revision as the LPC1800 Rev '-' and suffers the same limitation.  Our project has RMII working successfully on LPC4350 Rev 'A'so I suspect everything will be well again when you receive your new hardware.

BTW, we are using a fantastic PHY by Micrel: KSZ8031.  It is voltage mode drive PHY, meaning about 50 mA is saved by not having a bias current through the ethernet transformer that most PHYs have.

[lpcware]

Content originally posted in LPCWare by PhilYoung on Wed Apr 18 16:09:51 MST 2012
Thanks,
I already spotted the bug in the RMII setup code, but I'm using my own code for the setup, and I also have the correct pin settings as you stated. I verified all signal with a scope and see the TxEnable etc sent to the PHY but wireshark reports on packets from my board ( although the PHY register indicate it has succesfully negotiated a 100Mbps full duplex link).

NXP are shipping a board to me now so I'll test it tomorrow hopefully as I've wasted 2 days trying to get our board working in RMII mode. I used the Raptor-TC2 in MII mode and that worked but unfortunately I don't have access to the pins for MII mode on my board, I would reccommend at the moment that if you have the choice you lay out your board with the option of falling back to MII mode since I know that works.

clearly from the obvious bug in the example RMII code the example has only been tested in MII mode.

regards

Phil.

[lpcware]

Content originally posted in LPCWare by DPeters on Wed Apr 18 09:15:05 MST 2012
We are developing a custom PCB using LPC4350 and using RMII mode.  The example does have a bug, the PHY clock should be 50 MHz, not 25 MHz.  Be careful setting up the pinmuxing, to ensure the input buffer is enabled, and the input glitch filter is DISABLED for the PHY ref clock.  Make sure this is done after the command
 
    CGU_EnableEntity(CGU_CLKSRC_ENET_TX_CLK, ENABLE);

if using LPCWare CGU drivers because the CGU_EnableEntity() routine makes assumptions about pinmux settings that does not work with RMII.