Query on EMC CKE Pin Behavior During Controller Power-Up_LPC3250FET296

[Thirupathi]

Dear Team,

What should be the expected value of the EMC CKE pin when the controller is powered ON?

We are currently facing an issue while writing data to DDR2, and we are not observing a HIGH level on the CKE pin.

Could you please help us understand the expected behavior and possible reasons for this issue?

[Alice_Yang]

Hi @Thirupathi 

If what you are referring to is that CKE is not observed high immediately after the controller powers up, this can be a normal behavior, since the LPC32x0 does not assert the SDRAM clock enable signal after reset.

However, if you mean that CKE remains low even after the system has entered the DDR2 initialization or data write phase, please check:

1. Whether the initialization code has actually executed up to the EMC/DDR enable stage.
2.  Whether the official CKE workaround circuit is present and correctly connected.   https://www.nxp.com.cn/docs/en/errata/ES_LPC3250.pdf  
3. Whether the system has been reset during an SDRAM access, which could cause the SDRAM to remain stuck in its previous state.

Thank you.

BR

Alice