Creating a small custom board for testing out the LPC55S6 part. The datasheet and the eval board schematics show the connections for using the internal DCDC converter but nothing for bypassing it. The eval schematic does show how to supply external core voltage but that doesn't give the whole idea. I want to design around supplying the 1.2V? (that's the number I came across for running @ 150MHz) directly to the VDD_PMU from an LDO. The efficiency loss isn't a problem for our use case and it hopefully reduces noise too. So how will the connections look like now? My understanding:
1. Connect the output of a 1.2V LDO directly to the VDD_PMU pin, with some decoupling capacitors.
2. Leave the VBAT_PMU, VBAT_DCDC, LX and FB pins unconnected. This removes all the relevant decoupling caps and the power inductor.
3. VSS_PMU and VSS_DCDC are left connected to ground as before.
4. Eval board schematic uses two ferrite beads to separate into VDDA and IO's VDD domains. Is this needed now that there is no DCDC converter or was that placed for the sake of cleaner supply to ADC?
And does anything change on the software side of things? I would really appreciate a simple block diagram for this like the one mentioned in datasheet section 6.1.2 Using Internal DC-DC converter:
The AE team said that the internal DC/DC converter is strongly recommended, we have done full test for the solution including full temperature range test.
For the solution that customer uses external regulator to provide power for the VDD_PMU pin, we DO NOT recommend the solution, we do not provide any test for the solution till now.
First of all, there are two solutions to get power supply for the VDD_PMU pin, one is to use external LDO with 1.1V power supply voltage, even if you use external LDO, you have to connect the VBAT_PMU to another regulator, because a lot of peripherals are powered by the VBAT_PMU pin. Regarding the VBAT_DCDC pin in the case, I will consult to AE team, because there is a Deep_Sleep_LDO, I will confirm whether the Deep_Sleep_LDO is only powered by the VBAT_DCDC or VDD_PMU pin.
Another solution is to use internal buck DC/DC converter to provide power for the pin VDD_PMU, this is described in the above diagram.
Regarding the Ferrite bead, I think the ferrite bead between the VDDA and VDD_TARGET node is required in order to reduce the noise for the analog power supply, the ferrite bead between the VDD and VDD_TARGET node is not required.
Hope it can help you
1. Would supplying 1.2V instead of 1.1V be a problem?
2. Need to supply both VBAT_DCDC? and VBAT_PMU with 3.3V as before, no problem. But what about the FB and LX pins?
I would really appreciate a block diagram once you confirm the requirement for VBAT_DCDC and anything else. For now, It seems like it might be better to stick with DCDC converter as this seems to be undocumented. Please do add an app note or update the datasheet for the alternate circuit as it would help down the line.
I suggest you use 1.1V LDO for VDD_MPU pin, because the voltage range of VDD_MPU is from 1.0V to 1.2V, the 1.2V is the maximum value. Regarding the other pins connection when the LDO is used for the VDD_PMU pin, I will update after I get feedback from AE team.