Program Flash with Secure AHB Controller enabled

[simon_ott]

What is the proper way to read and write data from and to the flash?

I assumed that the FLASH API should be used, so I used those functions to read and write data to and from the flash (FLASH_Init, FLASH_Program, FLASH_Erase, ...). This worked fine, as long as the Secure AHB Controller is not enabled.

However, as soon as I enable the Secure AHB Controller, the LPC55S69 runs into a bus fault when calling FLASH_Init. I can see that the error is caused on AHB layer zero by the CPU (bus master 0) which is running secure privileged and that it is a read address on location 0x3004310 that causes the security violation. The address is obviously in the ROM area where the FLASH API is located, but I am not sure why I cannot access this region at all. Explicitely programming the security level of the ROM (AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] and so on) to any security level does not have any effect.

My only goal is to store some data structures persistently (while the Secure AHB Controller is enabled). So my question is if I am doing something wrong in general (use the wrong API etc.) or how can I prevent the security error when accessing the FLASH API.

[simon_ott]

Thank you for the reply. The SAU is configured but that was not the problem anyway. The error occured as soon as I enabled the Secure AHB Controller via the AHB_SECURE_CTRL MISC_CTRL_REG (ENABLE_SECURE_CHECKING bits set to 0x1).

However, I think I now solved the problem: I overlooked that the secure checking is in restrictive mode so that the master must have exactly the same tier as the slave (my thinking was that secure privileged can access anything). I configured the ROM where the FLASH API is located to be accessible from tier 3 (AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[x] = 0x33333333U;) before writing the MISC_CTRL_REG and now the flash can be programmed by secure privileged (tier 3) software without any errors.

What I was not able to find out: If a secure violation happens, the master number of the master that caused the violation can be read from the AHB_SECURE_CTRL->SEC_VIO_MISC_INFO register (SEC_VIO_INFO_MASTER bits). Number 0 seems to be CPU0, but I did not find a list of the other master numbers. Is this somewhere documented?

[Alice_Yang · Accepted solution]

Hello Simon,

Feedback as below: 

Check “Master secure level register (MASTER_SEC_LEVEL, offset = 0xFD0) bit description” should give you the master list:

0 – CPU0 CortexM33 code bus port

1 - CPU0 CortexM33 system bus port

2 – CPU1 CortexM33 code bus port

3 – CPU1 CortexM33 system bus port

4 - USB full speed Device

5 - System DMA 0.

6 - EZH data.

7 - EZH instruction.

8 – SDIO

9 - Power quad.

10 – Hash-Crypt engine

11 - USB full speed host.

12 - System DMA 1

Hope it helps,

Have a great day,
TIC

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[Alice_Yang]

Hello Simon,

In the Reference Manual, really lost the detail meaning of SEC_VIO_INFO_MASTER.

I have ask development team about this, will tell you after I get feedback .ASAP.

Sorry for the inconvenient to you .

 BR

Alice

[Alice_Yang]

Hello Simon Ott,

In order to analysis your question, could you please tell me:

1) How about " enable the Secure AHB Controller, "? Please show the enable code.

2) Which part of he memory you wan to read and write,? And how to configure the their secure rules?

3) Have you config the SAU and IDAU ? If yes, how to config?

BR

Alice