Content originally posted in LPCWare by aaram on Thu Feb 06 22:52:30 MST 2014
Hi to all,
I have configured 7 inches tft LCD with LPC1788 controller for 24 bit and it is working without any problem. but now i need to reconfigure it to 16bit. So I changed the value of BPP in LCD control register to 6 from 5. Now the letters and all the shapes in tft lcd got bigger(doubled).
When iam using 24bit in LCD I was using two hynix sdram of size 16Mx16 each. Now i reduced it to one. But stil it is not working. Can someone please me on this issue........
SDRAM CONFIGURATION:
#define DYN_CONTROL_NOP_COMMAND0x00000183
#define DYN_CONTROL_PALL_COMMAND0x00000103
#define DYN_CONTROL_MODE_COMMAND 0x00000083
#define DYN_CONTROL_NORMAL_COMMAND 0x00000000
#define EMC_CLOCK 60000000
#define NANO_SEC (1/1000000000)
#define NS_TO_CLKS(ns) ( (uint32_t)( (double)(ns) * EMC_CLOCK * NANO_SEC ) + 1 )
#define SDRAM_BASE_ADDRESS 0xA0000000 /* CS0 */
#define REFRESH_TIME_MAX 0X7FF
void sdram_initialization (void){
unsigned long Dummy;
LPC_SC->PCONP |= (1<<11);
emc_sdram_pin_allocation ();
LPC_SC->EMCDLYCTL = 0x00080808;
EMC_CONTROL = 0x00000001;
EMC_CONFIG = 0x00000000;
LPC_SC->EMCCLKSEL=0; //60 MHZ
EMC_DYN_REFERESH = REFRESH_TIME_MAX;/*260 usec*/
EMC_DYN_RASCAS0 = 0X00000303;
EMC_DYN_READ_CONFIG = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
EMC_DYN_RP = NS_TO_CLKS(18);
EMC_DYN_RAS = NS_TO_CLKS(42);
EMC_DYN_SREX = 1;
EMC_DYN_APR = 1;
EMC_DYN_DAL = 2+NS_TO_CLKS(18);
EMC_DYN_WR = 1;
EMC_DYN_RC = NS_TO_CLKS(63);
EMC_DYN_RFC = 4;
EMC_DYN_XSR = 1;
EMC_DYN_RRD = NS_TO_CLKS(15);
EMC_DYN_MRD = 2;
EMC_DYN_CONFIG0 = (1<<10) | (1<<9) | (1<<7);/* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */\
EMC_DYN_CONTROL = DYN_CONTROL_NOP_COMMAND;
delay_in_millisecond(100); /* wait 100ms */
EMC_DYN_CONTROL = DYN_CONTROL_PALL_COMMAND;
delay_in_millisecond(500);
EMC_DYN_REFERESH = NS_TO_CLKS(7812)>>4; //30 64ms/8192=7812 nsec
EMC_DYN_CONTROL = DYN_CONTROL_MODE_COMMAND;
Dummy = *((volatile uint32_t *)(SDRAM_BASE_ADDRESS | (0x33<<12)));
delay_in_millisecond(100);
EMC_DYN_CONTROL = DYN_CONTROL_NORMAL_COMMAND;
EMC_DYN_CONFIG0 |= 0x80000; /* enable buffer */
delay_in_millisecond(100);
}
7 INCHES TFT LCD CONFIGURATION:
#define TFT_H_SIZE 800
#define TFT_H_PULSE 2
#define TFT_H_FRONTPORCH 17
#define TFT_H_BACKPORCH 45
#define TFT_V_SIZE 480
#define TFT_V_PULSE 2
#define TFT_V_FRONTPORCH 22
#define TFT_V_BACKPORCH 22
#define LCD_EN (1<<0)
#define BPP 6
#define LCDTFT (1<<5)
#define BGR (1<<8)
#define LCDPWR (1<<11)
#define IVS (1<<11)
#define IHS (1<<12)
#define BCD (1<<26)
void glcd_initialization (){
unsigned long i;
unsigned long *pDst = (unsigned long *)LCD_VRAM_BASE_ADDR;
// IOCON_P0_4 = LCD_RED;
//IOCON_P0_5 = LCD_RED;
// IOCON_P4_28 = LCD_RED;
IOCON_P4_29 = LCD_RED;
IOCON_P2_6 = LCD_RED;
IOCON_P2_7 = LCD_RED;
IOCON_P2_8 = LCD_RED;
IOCON_P2_9 = LCD_RED;
// IOCON_P0_6 = LCD_GREEN;
// IOCON_P0_7 = LCD_GREEN;
IOCON_P1_20 = LCD_GREEN;
IOCON_P1_21 = LCD_GREEN;
IOCON_P1_22 = LCD_GREEN;
IOCON_P1_23 = LCD_GREEN;
IOCON_P1_24 = LCD_GREEN;
IOCON_P1_25 = LCD_GREEN;
// IOCON_P0_8 = LCD_BLUE ;
// IOCON_P0_9 = LCD_BLUE ;
// IOCON_P2_12 = LCD_BLUE ;
IOCON_P2_13 = LCD_BLUE ;
IOCON_P1_26 = LCD_BLUE ;
IOCON_P1_27 = LCD_BLUE ;
IOCON_P1_28 = LCD_BLUE ;
IOCON_P1_29 = LCD_BLUE ;
IOCON_P2_2 = LCD_DCLK ;
IOCON_P2_5 = LCD_HSYNC;
IOCON_P2_3 = LCD_VSYNC;
IOCON_P2_4 = LCD_LCDDEN;
IOCON_P2_0 = LCD_PWR;
LPC_SC->PCONP |= 1<<0;
LCD_CTRL_REG &= 0;
LCD_CTRL_REG |= (BPP<<1)|LCDTFT;
LCD_CTRL_REG &= ~BGR;
LCD_CTRL_REG &= ~LCDPWR;
LCD_POL_REG &= 0;
LCD_POL_REG |=(5<<0)|1<<6;
LCD_POL_REG |=IVS|IHS|BCD;
LCD_POL_REG |= (TFT_H_SIZE-1)<<16;
LCD_POL_REG |=(0<<27);
LPC_SC->LCD_CFG = 7 ;// 120000000 / ((unsigned long) C_GLCD_PIX_CLK); 15 MHZ
/*Refresh time 41msec*/
LCD_TIMH_REG &= 0;
LCD_TIMH_REG |= (TFT_H_BACKPORCH - 1)<<24;
LCD_TIMH_REG |= (TFT_H_FRONTPORCH - 1)<<16;
LCD_TIMH_REG |= (TFT_H_PULSE - 1)<<8;
LCD_TIMH_REG |= ((TFT_H_SIZE/16) - 1)<<2;
LCD_TIMV_REG &= 0;
LCD_TIMV_REG |= (TFT_V_BACKPORCH)<<24;
LCD_TIMV_REG |= (TFT_V_FRONTPORCH)<<16;
LCD_TIMV_REG |= (TFT_V_PULSE - 1)<<10;
LCD_TIMV_REG |= TFT_V_SIZE - 1;
LCD_UPBASE_REG = LCD_VRAM_BASE_ADDR & ~7UL ;
LCD_LPBASE_REG = LCD_VRAM_BASE_ADDR & ~7UL ;
for( i = 0; (TFT_H_SIZE * TFT_V_SIZE) > i; i++)
*pDst++ = White;
for(i = 10000; i; i--);
//LCD_CTRL_REG |= LCDPWR| LCD_EN;
LCD_CTRL_REG |= LCDPWR;//| LCD_EN;
}
void lcd_powerenable(){
LCD_CTRL_REG |= LCD_EN;
}
void lcd_powerdisable(){
LCD_CTRL_REG &= LCD_EN;
}