Placing LPC4367's M0SUB core's code in other memory location

[akhilesh_sreedh]

Hello,

I would like to know if LPC4367's M0SUB core's program can be placed in any other internal memory location apart from the 16kB LOCAL SRAM which the LPCXpresso project creation wizard configures by default,  since our code for M0SUB doesn't fit into the 16 kB LOCAL SRAM.

Also, I would like to know if only M0SUB can be made to access code from an external flash using the SPIFI or a parallel NOR flash.

Any examples regarding both the queries would help me. 

Thanks,

Akhilesh Sreedharan 

[bernhardfink · Accepted solution]

It's possible, the M0SUB is a bus master and can access any memory location in the LPC4367.

But as the M0SUB is behind a sync bridge, there will be a latency.

I think it is 4 wait states, so you will only get 25% performance compared to execution from the LOCAL 16+2kB SRAM.

You can access the SPIFI with the M0SUB, but not exclusively. There is no systemwide MPU in this chip, only the M4 has a memory protection unit. All other bust master with their DMA or the M0APP could also access the SPIFI, so you can't establish a firewall in order to keep the access exclusively to the M0SUB.

Regards,

Bernhard.