Content originally posted in LPCWare by farcaller on Fri Jun 13 07:51:43 MST 2014
I'm trying to write an algorithm that would pick the best available PLL0 configuration for the user, given F_in and F_cclk. For now, I don't care about USB clocking.
Let's say the user has mbed board (external 12MHz crystal) that he wants clocked at 100MHz, so the input is:
F_in = 12MHz
F_cclk = 100MHz
The manual says that I should pick higher F_ref if possible for a more stable PLL, for low frequency input clock. What is considered a "low frequency", though?
Also, I can get quite flexible with F_cco value, given that it's later passed through a divisor. So I have two flexibility points here:
[list]
[*] prefer higher M/N pair to lower M/N (i.e. prefer higher F_ref to lower F_ref)
[*] prefer higher F_cco/divisor to lower F_cco/divisor
[/list]
Is there any generic rule which one of those I should prefer? What is better, m=50, n=3, divisor=4, or, say, m=325, n=26, divisor=3?