Content originally posted in LPCWare by ezharkov on Fri Aug 30 13:03:40 MST 2013 Figure 2 shows two 16 kB banks, bank 0 and bank 1, I presume. They are on different ports, and that eliminates contention. I understand that. But my question was about the two 8 kB sections in the bank 0. Why are they documented as two separate 8 kB sections instead of one single 16 kB, like bank 1?
Content originally posted in LPCWare by usb10185 on Fri Aug 30 12:48:15 MST 2013 Hi,
The DMA should work across the boundaries assuming that the addressing is contiguous. The UM Figure 2 explains why there are different banks of SRAM - It allows for multi-master access to different banks without memory contention.