PLL1 MSEL doesn't multiply output frequency

[zack1]

I'm experimenting on a LPCXpresso4367.

After reading UM10503, I attempted to implement the M4 core clock initialization procedure described on page 167. I've attempted to measure this both ~directly via FREQ_MON and indirectly via delay-loops. Code for both is attached.

The behavior I observe is:

I selected an M-divider of 17 (0x10) and an N-divider of 1 (0x0), which I expect should yield 204MHz in DIRECT mode. I measure a quantized ~12MHz from both IRC and XTAL_OSC (expected), but the PLL1 output is also ~12Mhz. If I enable a P-divider of 2 (0x0), I observe ~6MHz as expected.

As far as I can tell, the P-divider and BASE_M4_CLK clock selection are working, but the frequency isn't multiplied, and modifying MSEL has effects that don't match my understanding of the description in the datasheet.

I also compared this to lpcopen (both the source code and the runtime register values), and I didn't see anything obviously suspicious that I'm missing from Chip_SetupCoreClock.

What am I missing?

[jeremyzhou]

Hi Zachary Buhman，
Thank you for your interest in NXP Semiconductor products and the opportunity to serve you.
To provide the fastest possible support，I'd highly recommend you to refer to the startup files, as in the files, it illustrates the how to set up the clock, of course, it includes how to configure PLL1.

Hope it helps.
Have a great day,
TIC

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