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MKE04

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Contributor IV

We are using Periodic Interrupt Timer in MKE04Z8VTG4 controller. While using PIT, facing a problem like, generating interrupt without reaching count to zero. Initializations are provided below:

 void pit_init()
{

CLOCK_EnableClock(kCLOCK_Pit0);
PIT->MCR = 0x01; // Enable clock for PIT
PIT->CHANNEL[0].LDVAL = 0x0003A9A6;

PIT->CHANNEL[0].TCTRL = 0x03; // Start Timer & Interrupt Enable
NVIC_EnableIRQ(PIT_CH0_IRQn);
NVIC_SetPriority(PIT_CH0_IRQn,0);

}

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Contributor IV

I have done the same thing sir.

but entering into PIT Handler even if counter is not set to zero.

Even the timing is also getting mismatch. from below calculation it should be 10msec, but it is set to 13msec.

Here BUS_CLOCK = 24MHz, PIT_INT = 10msec

void pit_init()
{
 pit_config.enableRunInDebug = false;
 

 PIT_Init(PIT, &pit_config);   // PIT PERIPHERAL RUNS ON BUS CLOCK, AS PER USER MANUAL
 
 
 PIT->MCR              = 0x00;                            // Enable clock for PIT
 PIT->CHANNEL[0].LDVAL = 240000;//(BUS_CLOCK*(PIT_INT/1000));      // LOAD VALUE FOR EVERY 10MSEC INTERRUPT
 PIT->CHANNEL[0].TCTRL = 0x03;                            // Start Timer & Interrupt Enable
 NVIC_EnableIRQ(PIT_CH0_IRQn);
 NVIC_SetPriority(PIT_CH0_IRQn,0);
 

}

void PIT_CH0_IRQHandler()
{
 PIT->CHANNEL[0].TFLG = 0x01;      // Disable Interrupt
 PIT->CHANNEL[0].TCTRL = 0x00;     // Disable timer & Stop timer
 PIT->CHANNEL[0].TCTRL = 0x03;       // Start Timer & Interrupt Enable

 count_l++;

 if(count_l >= LED_TOGGLE_VALUE)
 {   
  flag = flag^1;                                                                               
    GPIO_PortToggle(kGPIO_PORTB, 0x20);  // toggle led for every 500msec
   count_l = RESET;
 } 
 ADC_SetChannelConfig(ADC,&sADC_Config_1);
}

Please reply back..

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NXP TechSupport
NXP TechSupport

Hello Muralidhar,

In the following link if you download the SDK for the FRDM-KE06 (the SDK for the KE04 doesn't have examples available but the ones from the KE06 works for all the KE0x) you can find an example of how to configure the PIT timer.

Let me know if this helps you.

Best Regards,

Alexis Andalon 

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Contributor IV

Thank you Alexis Andalon, for your valuable replies..

The link was helpful.

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NXP TechSupport
NXP TechSupport

Hi Muralidhar M,

 

In the MCR register, the first bit that should be enabled is the MDIS.

pastedImage_4.png

Also, I will suggest to start the timer after the NVIC interruptions are enabled.

 

I hope this helps you.

Best Regards,

Alexis Andalon

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