MCUXpresso config tools eFlexPWM clock issue

[EnBono]

Hi,

I noticed a problem while trying to configure the PWM on the LPC55S36 using MCUXpresso config tools.

Comparing the PWM initialization from the config tools with the one present in the SDK (driver_examples/pwm), it seems that it's missing the enabling of PWM clock (Let's assume that i want to configure PWM0, submodule 0, the missing instruction is SYSCON->PWM0SUBCTL |= SYSCON_PWM0SUBCTL_CLK0_EN_MASK;)

I tried to search something both in peripherals configuration and clocks configuration but i can't find a way to enable that clock.

The only workaround i found is to add custom software initialization in peripherals configuration and add that instruction manually (Custom_sw_initialization_init function called before PWM0_init).

am i missing something from the config tools?

[xiangjun_rong]

Hi,

For LPC5536 and SDK package,I suppose that you can use the following api function to enable the PWM gated clock.

CLOCK_EnableClock(kCLOCK_Pwm0);

The kCLOCK_Pwm0 macro is defined in the fsl_clock.h.

I copy the macro:

typedef enum _clock_ip_name
{
kCLOCK_IpInvalid = 0U, /*!< Invalid IP name. */
kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */

kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3U), /*!< Clock gate name: Sram1. */

kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Sram2. */

kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5U), /*!< Clock gate name: Sram3. */

kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Sram4. */

kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Flash. */

kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8U), /*!< Clock gate name: Fmc. */

kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Flexspi. */

kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11U), /*!< Clock gate name: InputMux. */

kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Iocon. */

kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Gpio0. */

kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Gpio1. */

kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16U), /*!< Clock gate name: Gpio2. */

kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Gpio3. */

kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Pint. */

kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Gint. */

kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20U), /*!< Clock gate name: Dma0. */

kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21U), /*!< Clock gate name: Crc. */

kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22U), /*!< Clock gate name: Wwdt. */

kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23U), /*!< Clock gate name: Rtc0. */

kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26U), /*!< Clock gate name: Mailbox. */

kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27U), /*!< Clock gate name: Adc0. */

kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28U), /*!< Clock gate name: Adc1. */

kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29U), /*!< Clock gate name: Dac0. */

kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0U), /*!< Clock gate name: Mrt. */

kCLOCK_Ostimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1U), /*!< Clock gate name: Ostimer. */

kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2U), /*!< Clock gate name: Sct. */

kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7U), /*!< Clock gate name: Mcan. */

kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10U), /*!< Clock gate name: Utick. */

kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11U), /*!< Clock gate name: FlexComm0. */

kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12U), /*!< Clock gate name: FlexComm1. */

kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13U), /*!< Clock gate name: FlexComm2. */

kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14U), /*!< Clock gate name: FlexComm3. */

kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15U), /*!< Clock gate name: FlexComm4. */

kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16U), /*!< Clock gate name: FlexComm5. */

kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17U), /*!< Clock gate name: FlexComm6. */

kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18U), /*!< Clock gate name: FlexComm7. */

kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */

kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */

kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */

kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */

kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */

kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */

kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */

kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */

kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */

kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */

kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */

kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */

kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */

kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */

kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */

kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */

kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */

kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */

kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */

kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */

kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */

kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */

kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */

kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */

kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */

kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */

kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */

kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */

kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */

kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */

kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */

kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */

kCLOCK_Dmic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19U), /*!< Clock gate name: Dmic. */

kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22U), /*!< Clock gate name: Timer2. */

kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25U), /*!< Clock gate name: Usbd0. */

kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26U), /*!< Clock gate name: Timer0. */

kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27U), /*!< Clock gate name: Timer1. */

kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1U), /*!< Clock gate name: Dma1. */

kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2U), /*!< Clock gate name: Comp. */

kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8U), /*!< Clock gate name: Freqme. */

kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11U), /*!< Clock gate name: Cdog. */

kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13U), /*!< Clock gate name: Rng. */

kCLOCK_Pmux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14U), /*!< Clock gate name: Pmux1. */

kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15U), /*!< Clock gate name: Sysctl. */

kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16U), /*!< Clock gate name: Usbhmr0. */

kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17U), /*!< Clock gate name: Usbhsl0. */

kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18U), /*!< Clock gate name: Css. */

kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19U), /*!< Clock gate name: PowerQuad. */

kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21U), /*!< Clock gate name: Timer3. */

kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22U), /*!< Clock gate name: Timer4. */

kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23U), /*!< Clock gate name: Puf. */

kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24U), /*!< Clock gate name: Pkc. */

kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27U), /*!< Clock gate name: AnalogCtrl. */

kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28U), /*!< Clock gate name: Lspi. */

kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29U), /*!< Clock gate name: Sec. */

kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30U), /*!< Clock gate name: Int. */

kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0U), /*!< Clock gate name: I3c0. */

kCLOCK_Enc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3U), /*!< Clock gate name: Enc0. */

kCLOCK_Enc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4U), /*!< Clock gate name: Enc1. */

kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5U), /*!< Clock gate name: Pwm0. */

kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6U), /*!< Clock gate name: Pwm1. */

kCLOCK_Aoi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7U), /*!< Clock gate name: Aoi0. */

kCLOCK_Aoi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8U), /*!< Clock gate name: Aoi1. */

kCLOCK_Ftm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 9U), /*!< Clock gate name: Ftm0. */

kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 10U), /*!< Clock gate name: Dac1. */

kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11U), /*!< Clock gate name: Dac2. */

kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12U), /*!< Clock gate name: Opamp0. */

kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13U), /*!< Clock gate name: Opamp1. */

kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14U), /*!< Clock gate name: Opamp2. */

kCLOCK_Hscmp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15U), /*!< Clock gate name: Hscmp0. */

kCLOCK_Hscmp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 16U), /*!< Clock gate name: Hscmp1. */

kCLOCK_Hscmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 17U), /*!< Clock gate name: Hscmp2. */

kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18U) /*!< Clock gate name: Vref. */

} clock_ip_name_t;

Hope it can help you

BR

XiangJun Rong