LPC86x WKT clocking description is a mess

[sh9]

I refer to UM11607 Rev. 3, chapters 8 (SYSCON), 16 (PMU) and 23 (WKT). I am trying to figure out the clock tree as far as the WKT is concerned, and am finding contradictory information. The documentation is clearly incorrect.

It seems to me that the multiplexer WKT_CTRL shown in Fig 8 doesn't exist. Neither does the ÷128 divider shown for "Ipwr_clk_vulp from PMU". This also affects Fig 43, which I consider to at least be closer to the truth, in that the two multiplexers inside the WKT block appear to be real.

The verbal description in 23.5.1 may well be the most accurate - at least that's my impression. The "lp_osc_clk" signal (is that the same signal as "lp_osc"?) doesn't appear to have any bearing on the WKT, though, despite what is shown in both Fig 8 and 43.

Maybe there was some confusion between the low power oscillator and the ultra low power oscillator. Multiple places in the document seem to confuse them. For example, the WWDT is described as being clocked by the low power oscillator, yet in chapter 16.7.6.1 it is implied that it can be clocked from the ultra low power oscillator while in power-down mode. There likely are more instances of this confusion.

The description of the low power oscillator in chapter 8.6.5 is also garbled. The bitfields as decribed in the explanatory text don't match those described in table 76.

Allow me to finish with a question: There is a way to configure the FRO for different frequencies using an API call. But is there also a way to read back what the frequency was set to, or do I have to measure it against another clock source? And does this setting affect the frequency of the clock that goes to the WKT? In the WKT description it appears as a fixed 12 MHz source.

[sh9]

Thanks for your reply, Harry!

So the legend below the Multiplexer in Fig 43 should read WKTCLKSEL, which is the register name in 8.6.19 of the user manual. The bit should also be called WKTCLKSEL.

The frequency 12 MHz written beside the upper input of the multiplexer is also somewhat confusing. The FRO can operate at several different frequencies, so it is surprising that the frequency here should always be 12 MHz. If it is 12 MHz, and the output of the divider in the WKT is 750 kHz, the divider would be ÷16, but this is nowhere noted. If it is indeed ÷16, then selecting the lp_osc instead would result in a frequency of 62500 Hz, correct?

I also don't understand the ÷128 divider in Fig 8. How does this relate to Fig 43? What are the signals lpwr_clk_vulp and Iwpwr_clk_vulp when applied to Fig 43?

Thank you and kind regards

Stefan

[Harry_Zhang]

Hi @sh9 

1. the Multiplexer in Fig 43 and Fig 8 should read WKTCLKSEL, which is the register name in 8.6.19 of the user manual. The bit should also be called WKTCLKSEL.

Yes, we will update the RM.

2.I also don't understand the ÷128 divider in Fig 8. How does this relate to Fig 43? What are the signals lpwr_clk_vulp and Iwpwr_clk_vulp when applied to Fig 43?

The Iwpwr_clk_vulp should be the ULPOSC clock source which is about 10Khz. It is derived from low power oscillator (1Mhz, 128 divider) and can be used in low power mode.

3.The frequency 12 MHz written beside the upper input of the multiplexer is also somewhat confusing. The FRO can operate at several different frequencies, so it is surprising that the frequency here should always be 12 MHz. If it is 12 MHz, and the output of the divider in the WKT is 750 kHz, the divider would be ÷16, but this is nowhere noted. If it is indeed ÷16, then selecting the lp_osc instead would result in a frequency of 62500 Hz, correct?

The Fig43 seems not the correct clock tree for WKT, you can check below figure and the LPOSC should be ULPOSC which is 10Khz.

We will update the RM.

Thanks for your understanding.

BR

Harry

[sh9]

Hi Harry,

thanks for your last reply!

I have to say that you now confused me even more!

So far I was under the impression that the "low power oscillator" and the "ultra low power oscillator" were two separate things, yet you seem to say they are the same, or derived from each other! My understanding so far was:

The former ("LPOSC") is located in the SYSCON block, and controlled with the LPOSCCTRL register described in the user manual 8.6.5. It oscillates at a frequency around 1 MHz. The description given there, as I already noted, is inconsistent regarding the bitfields, but the overall gist is that this is an imprecise, but low power clock source.

The latter ("ULPOSC") is located in the PMU block, and controlled with some bits in the DPDCTRL. It operates at 10 kHz, and can be used while the LPOSC is stopped.

You have presented a picture in your message to correct Fig 43, and in this new picture the multiplexer WKTCLKSEL, which you have confirmed to exist, has disappeared! Is this not you contradicting yourself?

The same multiplexer from the original Fig 43 also appears in Fig 8, where its labeling is wrong, but at least the signals going into it and out of it seem to be correct. The ÷128 divider below it, however, still seems wrong. If its input signal comes from the PMU, it would be from the ULPOSC, and it therefore would divide 10 kHz by 128 to yield approximately 80 Hz, which sounds unlikely to me.

It seems I have to reverse engineer this to get clarity.

Thanks for your efforts!

Cheers

Stefan

[Harry_Zhang]

Hi @sh9 

I have confirmed with our internal team.

you can follow below figure.

The ULPOSC is from the LPOSC.

We will change lp_osc to ulp_osc.

Thanks for your understanding.

BR

Harry

[sh9]

Hi Harry,

I now have gone through the trouble of reverse engineering the clocking structure. I have to say that your internal team doesn't seem to know the truth here, either. There does appear to be considerable confusion regarding what the actual internal wiring of the chip is. Here's what I have determined experimentally on my hardware using the LPC865M201JHI48. I did this by using a debugger to access the various registers, and a digital oscilloscope to measure frequencies.

1. The multiplexer shown in Fig. 8 is present, and it is controlled by the register WKTCLKSEL in the SYSCON block. The legend beside the multiplexer is therefore wrong, it should not refer to WKT_CTRL! Interestingly, inside the multiplexer symbol there are two bits shown for selecting the source, and indeed the WKTCLKSEL register has two working bits, although the register description in Table 90 only documents one, also named WKTCLKSEL. This appears to be the same multiplexer that is shown in Fig 43, where its legend is also wrong.
2. The two multiplexers in Fig 43 located inside the WKT block are also both present. They are controlled by bits in the register CTRL described in Table 385. The description there is largely correct, except that when bit CLKSEL is set to 0, the selected clock could be either derived from FRO or from LPOSC, depending on the multiplexer described above in point 1. The divider depicted in Fig 43 appears to divide by 16. Therefore, the frequency of 750 kHz annotated beside it, is not necessarily correct. If the LPOSC is selected, it is much lower.
3. The ULPOSC appears to be a completely separate oscillator that is unrelated to LPOSC, because LPOSC can be powered down with bit LPOSC_PD in register PDRUNCFG (Table 118), and the ULPOSC output clock remains active. This is also plausible because of the fact that the ULPOSC resides in the PMU, and not the SYSCON. The ULPOSCEN bit in register DPDCTRL (Table 235) controls the ULPOSC as expected, with no influence on the LPOSC.
4. I still have no idea what the ÷128 divider in Fig 8 is for, or whether it even exists. It is clear that it has nothing to do with dividing down the LPOSC signal to yield the ULPOSC signal, since the two oscillators are independent.
5. The LPOSCCTRL register description in 8.6.5 is simply wrong. The register appears to exist, but its reset value isn't 0x0. Apparently some process initializes it so that the LPOSC output frequency is approximately 1 MHz. It could be the ROM bootloader. The LPC865.svd file, interestingly, omits this register. Its description should be rewritten from scratch.
6. I'm intrigued by the LPOSCEN register described in Table 93. One bit appears to affect the WDT, and the other the WKT, which makes me wonder what the rationale behind it was, given that the other bits affecting the WKT are in the CTRL register there. The bits in LPOSCEN aren't mentioned anywhere else. It would be good to have a proper description of their purpose and function.

As you see, there are mistakes in various places, and this makes the description very confusing. There is definitely a case for overhauling the entire description of the clock tree as it relates to the WKT and the ULPOSC in the manual.

Kind regards

Stefan

[Harry_Zhang]

Hi @sh9 

We have tested this use case in our side.

Based on my test result, the wake timer function can match with below block diagram.

BR

Harry

[Harry_Zhang]

Hi @sh9 

Thanks for your information.

Our internal team is currently confirming this.

BR

Harry

[Harry_Zhang]

Hi @sh9 

Thanks for your information.

1. "It seems to me that the multiplexer WKT_CTRL shown in Fig 8 doesn't exist."

No, It exists. 

2. "The "lp_osc_clk" signal is that the same signal as "lp_osc"?"

Yes, the lp_osc_clk it the same with the lp_osc.

But the PDRINCFG0 is wrong in RM, it should be PDRUNCFG. We will modify this as soon as possible in RM.

3."it is implied that it can be clocked from the ultra low power oscillator while in power-down mode. There likely are more instances of this confusion."

When you enable the ultra low-power oscillator for use with the 10 kHz self-wake-up
timer clock. You must set this bit if the CLKSEL bit in the self-wake-up timer
CTRL bit is set.

BR

Harry