LPC845 PINT Interrupt latency

[xs_graziano]

Hello, 

I'm developing an application with tight constrains.

My problem is related to PINT latency. For my understanding the typical latency time for an interrupt in an arm Cortex M0+ is around 15 clock cycle. My clock is at 30Mhz. 

So I would expect something between 0.5 and 1uSec latency. 

I have measured the time between the signal and the interrupt levering up a pin immediatly after the interrupt head, and actually I got 7uSecs. 

Checking the assembler I can just see few instructions (less than 10) at the head of the interrupt.

The PINT interrupt is the only one with a 0 priority.

Is that normal or I'm doing something wrong?

Thank to anyone answering,

[xs_graziano]

Hi @carlos_o , thank for your answer. 

I'm using a custom hardware. I made the measure using a square wave generator, at 2400Hz, with the output connected to a pin of the LPC. The first instruction entering the irq change the status of another pin. Than I have a scope with two probes: one on the input pin, and the other on the out. I measure the time difference between the two fronts.

Really I've lost the IRQLATENCY register! Thank you to point it out. Actually it has the default configuration at 0x10.

The input filter in the pin is disabled, but I've activated the Hysteresis.

For my understanding the GPIO is managed at the same freq then the core, and it requires 1 cycle to change the status of a pin. I suppose is the same with the input. I have a question: from the datasheet, seems that the GPIO is directly connected to the Core, bypassing the BUS, but the BUS is required for instruction and data access. So, if the DMA is using the Bus for a burst transfer, can be an interrupt be retarded? 

Thank you

[xs_graziano]

I have made some more checks. Setting the pin high and than immediately low takes 4 asm instruction for a total of at most 5 clock cycles. I have got 255 nSecs, that is compatible with a clock of 20Mhz (I would have expected ca 160 nSecs).

So, I've set up the main clock as clockout on a pin, and I got a clear 30Mhz on the scope.

The system is configured for a 30Mhz FRO as main clock and the SYSAHBCLKDIV is set to 1 (one), so no div.

 Could be it's core is running at a lower clock frequency also if the main clock, at the clockout output (enbled via SYSCON) is showing 30Mhz?

Or something is slowing down the core?

... I think I've found part of the matter: the core is slowed down by the FLASH access time. Changing the Flash access time give a big improvement. 

But I don't have seen any details about the minimum guaranties access time in the datasheet, or it's condition.

If the instruction time improved, the interrupt latency is better (now 5uSec with 2 system clock access time for flash) but still far from the expectation.

[carlos_o]

Hi @xs_graziano 

Thank you for your post

Could you please confirm if you are using a custom board? if not, please specify which board you are using.

Please share how are you doing the measurement of timing to the interrupt get triggered.

Did you do any modification to the IRQLATENCY register? 

BR

Carlos