LPC824 ADC issues

[dlaw2]

The LPC824 ADC hardware triggers are listed incorrectly in LPCOpen (adc_8xx.h). For example, trigger 3 is supposed to be SCT_OUT3, but LPCOpen has"#define ADC_SEQ_CTRL_HWTRIG_CT16B0_MAT0  (3 << 12)".

Secondly, where can I find documentation on ADC timing? In particular, I would like to know how many ADC clock cycles it takes the ADC to execute a single-channel conversion, and whether any additional cycles are consumed to multiplex between channels in burst mode. I cannot find a timing diagram in the user manual or datasheet. The information present in the "static characteristics" section of the datasheet is inadequate because it only specifies the maximum operating frequency of the ADC.

[dlaw2]

Thank you for the response. It would be nice if that information appeared in the datasheet.

Will you be able to correct the LPCOpen error in a future release?

[ianbenton]

It's on the last line of section 21.5 in the user manual (not the datasheet). But I haven't checked whether it is 25 or 26 cycles!

[jeremyzhou]

Hi David Lawrence,

Thanks for your reply.

Yes, I'll report this "bug" to the LPCOpen team for checking.
Have a great day,
Best regards,

Ping

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[kylesmith2]

As far as I can tell, the 25 cycles listed in the user guide is incorrect, and should be 26. I have a circuit using DMA to transfer continuous ADC conversions to a ping-pong buffer, and have the DMA interrupt toggle an output pin. My clock speed is 30MHz +- 10ppm, and the ping-pong buffers store 120 conversion results each. If the 25 cycle timing was correct, I would expect the ADC to convert at exactly 1.2Msps, and the DMA interrupt to toggle the output every 100us. Instead, the output is toggled exactly every 104us (104.000us +- 0.001us). This is exactly 26 clock cycles per conversion, not 25.

[jeremyzhou]

Hi David Lawrence,

Thank you for your interest in NXP Semiconductor products and the opportunity to serve you.

1) I would like to know how many ADC clock cycles it takes the ADC to execute a single-channel conversion, and whether any additional cycles are consumed to multiplex between channels in burst mode?

It will 25 cycle to compete one conversion, it's also identical in the burst mode.

Hope this is clear.
Have a great day,
Ping

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