dear NXP,
I use the LPC55s69 development secure project.
I can run the secure demo whitch the code is in flash. the scat file just like below:
#define m_interrupts_start 0x10000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x10000200
#define m_text_size 0x0000FC00
#define m_veneer_table_start 0x1000FE00
#define m_veneer_table_size 0x200
#define m_data_start 0x30010000
#define m_data_size 0x00008000
but if I change to SRAM0 just like bellow, it can not run.
#define m_interrupts_start 0x30000000
#define m_interrupts_size 0x00000200
#define m_text_start 0x30000200
#define m_text_size 0x0000FC00
#define m_data_start 0x30010000
#define m_data_size 0x00008000
#define m_veneer_table_start 0x3000FE00
#define m_veneer_table_size 0x200
aflter load .elf, I can use the cmd "PC = 0x30004040" ,set pc
but when run to "PUSH {r7,lr}", whitch is the first instructions in “SystemInit” .it make a hardfault, I can see the "SCB--CFSR" is 0x0010, that's is a stack overflow.
Can't core0 run in SRAM0~4? It only can run in flash/Rom/SramX？
what about the Core1 ?
Hi, LiYou
Pls refer to the following Fig in Chapter 1 in UM11126.pdf, the Flash/ROM/SRAMX are connected to code bus directly, so core can execute code saved in Flash/ROM/SRAMX directly.
If you want to execute code in SRAM0, SRAM1,SRAM2, SRAM3, I suppose it is okay, but you have to configure the MPU module.
You can refer to the AN12423.pdf on how to set up MPU.
https://www.nxp.com.cn/docs/en/application-note/AN12423.pdf
Hope it can help you
So Core1 can run on SRAM without any other set because there is no MPU ?
Hi,
I have tried to test the code to run in SRAM0,SRAM1..., I confirm that there is not any problem to run in RAM0, RAM1,RAM2,RAM3, it is not necessary to initialize MPU.
I use the led_blinky of LPC55S69 project, and modify the code as following. The result is LED can toggle. The __RAMFUNC(RAM1) void toggle_Led(void) is put in RAM0
BR
XiangJun Rong
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cr_section_macros.h>
#include "board.h"
#include "pin_mux.h"
#include "fsl_power.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_LED_PORT BOARD_LED_BLUE_GPIO_PORT
#define BOARD_LED_PIN BOARD_LED_BLUE_GPIO_PIN
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
volatile uint32_t g_systickCounter;
/*******************************************************************************
* Code
******************************************************************************/
void SysTick_Handler(void)
{
if (g_systickCounter != 0U)
{
g_systickCounter--;
}
}
void SysTick_DelayTicks(uint32_t n)
{
g_systickCounter = n;
while (g_systickCounter != 0U)
{
}
}
void toggle_Led(void);
/*!
* @brief Main function
*/
int main(void)
{
/* Init output LED GPIO. */
GPIO_PortInit(GPIO, BOARD_LED_PORT);
/* Board pin init */
/* set BOD VBAT level to 1.65V */
POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false);
BOARD_InitPins();
SystemCoreClockUpdate();
/* Set systick reload value to generate 1ms interrupt */
if (SysTick_Config(SystemCoreClock / 1000U))
{
while (1)
{
}
}
while (1)
{
/* Delay 1000 ms */
SysTick_DelayTicks(1000U);
// GPIO_PortToggle(GPIO, BOARD_LED_PORT, 1u << BOARD_LED_PIN);
toggle_Led();
}
}
__RAMFUNC(RAM1) void toggle_Led(void)
{
GPIO_PortToggle(GPIO, BOARD_LED_PORT, 1u << BOARD_LED_PIN);
}
Hi, Frank,
How are you!
As the screenshot, the XN bit determines if you enable a space to be instruction fetch enabled or disabled.
Because I have not the Cortex-CM33 user guide, I attach the Cortex-M4 user guide.
BR
XiangJun Rong
