Hello,
It is my first post on this forum, so hello to everyone.
I'm starting the adventure with LPC55xx processors and have some beginner questions.
I analyze one example (SDK project lpcxpresso55s28_dev_audio_speaker_bm) and found such sequence:
CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);
Why divider is set to 1 and reset, and then set to 2 but without reset?
Why is it not set to 2 at once?
In SDK API Reference Manual I don't find an explanation.
Regards,
JarekC
Hello Jaroslaw Czula,Jaroslaw Czula
It seems when config PLL divider , we'd better first reset the divider counter.
Others can directly config divider.
BR
Alice