LPC55S69: enable SRAM clocks

[EugeneHiihtaja]

Hi !

For worj with USB SRAM I should enable clock kCLOCK_UsbRam1 explictly in my code e.g. CLOCK_EnableClock(kCLOCK_UsbRam1). ConfigTool is also not generate this line in any mode.

But what about other SRAM /flash section and Flash ?

There are mentioned in clock_ip_t enumeration

kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),

Are the enabled by default ? Or BootROM enable those.

Or the managed by some PowerLib API or ROM api.

How to undestand ?

Regards,

Eugene

[diego_charles]

Hi Eugene!

I am working on your question.

Please, provide me additional time to check

Regards,

Diego.

[diego_charles]

Hi Eugene!

Thank you for your patience,

On  the beginning of your application their controllers are already enabled by default, as we can see

on the following screenshot

Regards,

Diego

[EugeneHiihtaja]

Hi diego.charles‌ !

I can see in UM, default value for AHBCLKCTRL0 register is specified. It means SRAMn clocks enabled somewhere in bootrom. In this case is difficult to  trust if clocks always will be enabled there ( or disabled/enabled again ) and SRAM retain over reboot in next versions of bootrom if any.

By the way, I haven't found any clock enable for SRAM X area. Is this type of SRAM  always ON or it is just in other registers ?

But I think it is good idea to have clear spec. in what states registers remains after bootrom.

Regards,

Eugene

[diego_charles]

Hi Eugene,

You should not worry about the SRAM X areas, they are enabled by default.

As you know, you could control their retention state during low power modes using the sram_retention_ctrl register.

Regards,

Diego