Hi, Eugene,
Pls refer to the following part, the MPU, SysTick timer, and some of the registers in the System Control Block (SCB) are
also banked. In other words, secure and NON-secure SCB use different address.
I suggest you refer to the SDK example "lpcxpresso55s69_hello_world_s" in SDK, refer to file core_cm33.h, it defines different struct for secure and non-secure for SCB.
1. secure
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
2.non-secure.
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
1.3.3 Banked internal resources
Several internal resources are banked between Secure and Non-secure states.
For registers inside the processor core:
• The Stack Pointers are banked between Secure and Non-secure states. This enables separations of
Secure and Non-secure stacks.
• Interrupt masking registers like PRIMASK, FAULTMASK, and BASEPRI are banked.
• FAULTMASK and BASEPRI are available on the ARMv8-M architecture with Main Extension only.
This allows existing software to be reused, but Non-secure software cannot influence the operation of
Secure software.
• Bit 0 and 1 of the special CONTROL register are banked. Secure and Non-secure software can have
different Stack Pointer control and privileged settings.
In addition, the MPU, SysTick timer, and some of the registers in the System Control Block (SCB) are
also banked. For example, the Vector Table Offset Register (VTOR) is banked to allow the vector tables
for Secure software and Non-secure software to be separated. Software that accesses these registers using
an existing address accesses the corresponding view of the peripheral based on the current processor
state. Secure accesses see Secure peripherals. Non-secure accesses see Non-secure peripherals. Secure
software can also access Non-secure versions of these components using alias addresses.
The following figure shows the system control and debug area of a typical memory map:
Especially, pls refer to tzm_config.c for the SCB initialization.
Hope it can help you
BR
XiangJun Rong
